diff options
author | Jack Steiner <steiner@sgi.com> | 2005-12-22 13:45:41 -0600 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2006-01-13 14:10:06 -0800 |
commit | cfbb1426bd76c4ba6ec4491c8df2a5dd3d984750 (patch) | |
tree | 4fe639274b651ea77c9130eae0ccca36e16d6d17 /arch/ia64/sn/pci | |
parent | 17e8ce0e9417eee1f57f9b3d4aad168425e043c3 (diff) |
[IA64] Hole in IA64 TLB flushing from system threads
I originally thought this was an bug only in the SN code, but I think I
also see a hole in the generic IA64 tlb code. (Separate patch was sent
for the SN problem).
It looks like there is a bug in the TLB flushing code. During context switch,
kernel threads (kswapd, for example) inherit the mm of the task that was
previously running on the cpu. Normally, this is ok because the previous context
is still loaded into the RR registers. However, if the owner of the mm
migrates to another cpu, changes it's context number, and references a
page before kswapd issues a tlb_purge for that same page, the purge will be
done with a stale context number (& RR registers).
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/sn/pci')
0 files changed, 0 insertions, 0 deletions