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authorGreg Ungerer <gerg@uclinux.org>2009-05-19 14:38:08 +1000
committerGreg Ungerer <gerg@uclinux.org>2009-09-16 09:43:50 +1000
commitf2154bef817ac3d0ea67b52526fd8e88898b66f9 (patch)
tree3ffa5cf5c3ec82a59f75728a580bd9332a32ebee /arch/m68k/include/asm/m5206sim.h
parent5187995f0a9253e915dfee83684eae7b692213e6 (diff)
m68knommu: merge old ColdFire interrupt controller masking macros
Currently the code that supports setting the old style ColdFire interrupt controller mask registers is macros in the include files of each of the CPU types. Merge all these into a set of real masking functions in the old Coldfire interrupt controller code proper. All the macros are basically the same (excepting a register size difference on really early parts). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5206sim.h')
-rw-r--r--arch/m68k/include/asm/m5206sim.h16
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 7be8a2d3e65..b50061aaf8f 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -117,21 +117,11 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
-#if defined(CONFIG_M5206e)
-#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */
-#endif
-
/*
- * Macro to get and set IMR register. It is 16 bits on the 5206.
+ * Let the common interrupt handler code know that the ColdFire 5206*
+ * family of CPU's only has a 16bit sized IMR register.
*/
-#define mcf_getimr() \
- *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr) \
- *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
-
-#define mcf_getipr() \
- *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
+#define MCFSIM_IMR_IS_16BITS
/****************************************************************************/
#endif /* m5206sim_h */