diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-25 16:25:48 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-25 16:25:48 +0200 |
| commit | 7670c7010c7b367ca40c3aba02afb36149764a6e (patch) | |
| tree | 9f778e3bc3cb4270a60652c3a9731a5287954965 /arch/m68k/include/asm/m520xsim.h | |
| parent | 0110bba5e7731524940f9e02ce3d4aae75087f68 (diff) | |
| parent | dbcbf5885aa5a1ce6cbea72acbee100c0482be26 (diff) | |
Merge branch 'for-linus' of git://github.com/gregungerer/m68knommu
* 'for-linus' of git://github.com/gregungerer/m68knommu:
m68k: drop unused Kconfig symbols
m68k: drop unused Kconfig symbols
m68knommu: create common externs for _ram* vars
m68knommu: remove extern declarations of memory_start/memory_end from mm/init
m68knommu: use generic section names in mm/init code
m68knommu: use generic section names in setup code
m68k: merge the mmu and non-mmu traps.c files
m68k: move hardware vector setting from traps.c to its own file
m68k: merge mmu and non-mmu include/asm/entry.h files
m68k: merge the mmu and non-mmu kernel/Makefiles
m68k: merge mmu and non-mmu arch Makefiles
m68k: reorganize Kconfig options to improve mmu/non-mmu selections
m68knommu: fix problems with SPI/GPIO on ColdFire 520x
m68k: fix memcpy to unmatched/unaligned source and dest on 68000
Diffstat (limited to 'arch/m68k/include/asm/m520xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m520xsim.h | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index b6bf2c518ba..eda62de7e60 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -90,15 +90,13 @@ #define MCFGPIO_PDDR_FECH 0xFC0A4013 #define MCFGPIO_PDDR_FECL 0xFC0A4014 -#define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A -#define MCFGPIO_PPDSDR_BE 0xFC0A401B -#define MCFGPIO_PPDSDR_CS 0xFC0A401C -#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D -#define MCFGPIO_PPDSDR_QSPI 0xFC0A401E -#define MCFGPIO_PPDSDR_TIMER 0xFC0A401F -#define MCFGPIO_PPDSDR_UART 0xFC0A4021 -#define MCFGPIO_PPDSDR_FECH 0xFC0A4021 -#define MCFGPIO_PPDSDR_FECL 0xFC0A4022 +#define MCFGPIO_PPDSDR_CS 0xFC0A401A +#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B +#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C +#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D +#define MCFGPIO_PPDSDR_UART 0xFC0A401E +#define MCFGPIO_PPDSDR_FECH 0xFC0A401F +#define MCFGPIO_PPDSDR_FECL 0xFC0A4020 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 #define MCFGPIO_PCLRR_BE 0xFC0A4025 @@ -113,11 +111,11 @@ /* * Generic GPIO support */ -#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL -#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL -#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL +#define MCFGPIO_PODR MCFGPIO_PODR_CS +#define MCFGPIO_PDDR MCFGPIO_PDDR_CS +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS +#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS +#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS #define MCFGPIO_PIN_MAX 80 #define MCFGPIO_IRQ_MAX 8 |