diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2009-05-19 14:38:08 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-16 09:43:50 +1000 |
| commit | f2154bef817ac3d0ea67b52526fd8e88898b66f9 (patch) | |
| tree | 3ffa5cf5c3ec82a59f75728a580bd9332a32ebee /arch/m68k/include/asm/m5407sim.h | |
| parent | 5187995f0a9253e915dfee83684eae7b692213e6 (diff) | |
m68knommu: merge old ColdFire interrupt controller masking macros
Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5407sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5407sim.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 25194756b43..3c4bd5f08cd 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -97,19 +97,6 @@ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ /* - * Macro to set IMR register. It is 32 bits on the 5407. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - - -/* * Some symbol defines for the Parallel Port Pin Assignment Register */ #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ |