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authorGreg Ungerer <gerg@uclinux.org>2011-12-24 14:36:27 +1000
committerGreg Ungerer <gerg@uclinux.org>2012-03-05 09:43:10 +1000
commit440f6ffc061a84e81386a093c07af8a429c18702 (patch)
treea5c202d9b43364b57acbef2e9e745c78c8d1b79e /arch/m68k/platform/5307/config.c
parentc05793c7332d0f4179068bc6a6120e67b73a09ef (diff)
m68knommu: move old ColdFire timers init from CPU init to timers code
The original ColdFire timer interrupt setup is used by most of the users of the original ColdFire timer code. But the code is currently duplicated in each of the ColdFire CPU specific init files. Move it to the timers code that it is really part of. It is strait forward to make it conditional on also having the original interrupt engine that it needs. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/platform/5307/config.c')
-rw-r--r--arch/m68k/platform/5307/config.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/5307/config.c
index 89722cdbd02..5f4bf6cb017 100644
--- a/arch/m68k/platform/5307/config.c
+++ b/arch/m68k/platform/5307/config.c
@@ -28,23 +28,6 @@ unsigned char ledbank = 0xff;
/***************************************************************************/
-static void __init m5307_timers_init(void)
-{
- /* Timer1 is always used as system timer */
- writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
- MCF_MBAR + MCFSIM_TIMER1ICR);
- mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
-
-#ifdef CONFIG_HIGHPROFILE
- /* Timer2 is to be used as a high speed profile timer */
- writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
- MCF_MBAR + MCFSIM_TIMER2ICR);
- mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
-#endif
-}
-
-/***************************************************************************/
-
void m5307_cpu_reset(void)
{
local_irq_disable();
@@ -67,7 +50,6 @@ void __init config_BSP(char *commandp, int size)
mach_reset = m5307_cpu_reset;
mach_sched_init = hw_timer_init;
- m5307_timers_init();
/* Only support the external interrupts on their primary level */
mcf_mapirq2imr(25, MCFINTC_EINT1);