diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-17 09:52:43 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-17 09:52:43 -0700 |
commit | 66bc4a6f34a950c7aede597c578352c3eba82017 (patch) | |
tree | d8005bd9abc0209cff47072d7e48cf19fddc52f5 /arch/m68knommu/platform/68328/ints.c | |
parent | 96c015b75feaaa67c8744229937bd9c35919d16b (diff) | |
parent | 2985709d7f3078c7609ae7f16affc0fb478d7d7a (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (53 commits)
m68knommu: Make PAGE_SIZE available to assembly files.
m68knommu: fix ColdFire definition of CLOCK_TICK_RATE
m68knommu: set multi-function pins for ethernet when enabled
m68knommu: remove special interrupt handling code for ne2k support
m68knommu: relax IO_SPACE_LIMIT setting
m68knommu: remove ColdFire direct interrupt register access
m68knommu: create a speciailized ColdFire 5272 interrupt controller
m68knommu: add support for second interrupt controller of ColdFire 5249
m68knommu: clean up old ColdFire timer irq setup
m68knommu: map ColdFire interrupts to correct masking bits
m68knommu: clean up ColdFire 532x CPU timer setup
m68knommu: simplify ColdFire "timers" clock initialization
m68knommu: support code to mask external interrupts on old ColdFire CPU's
m68knommu: merge old ColdFire interrupt controller masking macros
m68knommu: remove duplicate ColdFire mcf_autovector() code
m68knommu: move ColdFire INTC definitions to new include file
m68knommu: mask off all interrupts in ColdFire intc-simr controller
m68knommu: remove timer device interrupt setup for ColdFire 532x
m68knommu: remove interrupt masking from ColdFire pit timer
m68knommu: remove unecessary interrupt level setting in ColdFire 520x setup
...
Diffstat (limited to 'arch/m68knommu/platform/68328/ints.c')
-rw-r--r-- | arch/m68knommu/platform/68328/ints.c | 72 |
1 files changed, 40 insertions, 32 deletions
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c index 72e56d554f4..b91ee85d4b5 100644 --- a/arch/m68knommu/platform/68328/ints.c +++ b/arch/m68knommu/platform/68328/ints.c @@ -73,34 +73,6 @@ extern e_vector *_ramvec; /* The number of spurious interrupts */ volatile unsigned int num_spurious; -/* - * This function should be called during kernel startup to initialize - * the machine vector table. - */ -void __init init_vectors(void) -{ - int i; - - /* set up the vectors */ - for (i = 72; i < 256; ++i) - _ramvec[i] = (e_vector) bad_interrupt; - - _ramvec[32] = system_call; - - _ramvec[65] = (e_vector) inthandler1; - _ramvec[66] = (e_vector) inthandler2; - _ramvec[67] = (e_vector) inthandler3; - _ramvec[68] = (e_vector) inthandler4; - _ramvec[69] = (e_vector) inthandler5; - _ramvec[70] = (e_vector) inthandler6; - _ramvec[71] = (e_vector) inthandler7; - - IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */ - - /* turn off all interrupts */ - IMR = ~0; -} - /* The 68k family did not have a good way to determine the source * of interrupts until later in the family. The EC000 core does * not provide the vector number on the stack, we vector everything @@ -163,18 +135,54 @@ void process_int(int vec, struct pt_regs *fp) } } -void enable_vector(unsigned int irq) +static void intc_irq_unmask(unsigned int irq) { IMR &= ~(1<<irq); } -void disable_vector(unsigned int irq) +static void intc_irq_mask(unsigned int irq) { IMR |= (1<<irq); } -void ack_vector(unsigned int irq) +static struct irq_chip intc_irq_chip = { + .name = "M68K-INTC", + .mask = intc_irq_mask, + .unmask = intc_irq_unmask, +}; + +/* + * This function should be called during kernel startup to initialize + * the machine vector table. + */ +void __init init_IRQ(void) { - /* Nothing needed */ + int i; + + /* set up the vectors */ + for (i = 72; i < 256; ++i) + _ramvec[i] = (e_vector) bad_interrupt; + + _ramvec[32] = system_call; + + _ramvec[65] = (e_vector) inthandler1; + _ramvec[66] = (e_vector) inthandler2; + _ramvec[67] = (e_vector) inthandler3; + _ramvec[68] = (e_vector) inthandler4; + _ramvec[69] = (e_vector) inthandler5; + _ramvec[70] = (e_vector) inthandler6; + _ramvec[71] = (e_vector) inthandler7; + + IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */ + + /* turn off all interrupts */ + IMR = ~0; + + for (i = 0; (i < NR_IRQS); i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].chip = &intc_irq_chip; + } } |