diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 15:31:08 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:20 +1000 |
| commit | 0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a (patch) | |
| tree | 01ffb12226fef2f4de5f3408e21fe64e19b5a522 /arch/m68knommu | |
| parent | d475e3e4739ce465df740b51decbbea3b1b51823 (diff) | |
m68knommu: support version 2 ColdFire split cache
The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
| -rw-r--r-- | arch/m68knommu/Kconfig | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index e6f482d18d0..61c29081b99 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -79,6 +79,9 @@ config COLDFIRE_SW_A7 bool default n +config HAVE_CACHE_SPLIT + bool + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -124,12 +127,14 @@ config M5206e config M520x bool "MCF520x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5207/5208 processor support. config M523x bool "MCF523x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5230/1/2/4/5 processor support @@ -141,6 +146,7 @@ config M5249 config M5271 bool "MCF5271" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5270/5271 processor support. @@ -152,12 +158,14 @@ config M5272 config M5275 bool "MCF5275" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5274/5275 processor support. config M528x bool "MCF528x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Motorola ColdFire 5280/5282 processor support. @@ -250,6 +258,30 @@ config OLDMASK Build support for the older revision ColdFire 5307 silicon. Specifically this is the 1H55J mask revision. +if HAVE_CACHE_SPLIT +choice + prompt "Split Cache Configuration" + default CACHE_I + +config CACHE_I + bool "Instruction" + help + Use all of the ColdFire CPU cache memory as an instruction cache. + +config CACHE_D + bool "Data" + help + Use all of the ColdFire CPU cache memory as a data cache. + +config CACHE_BOTH + bool "Both" + help + Split the ColdFire CPU cache, and use half as an instruction cache + and half as a data cache. +endchoice + +endif + comment "Platform" config PILOT3 |