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authorManuel Lauss <mano@roarinelk.homelinux.net>2008-12-21 09:26:23 +0100
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 09:57:27 +0000
commit0c694de12b54fa96b9555e07603f567906ce21c8 (patch)
treec7528273c1d86069cb6e83bd2b36706f663f1eb2 /arch/mips/alchemy/common/power.c
parent779e7d41ad004946603da139da99ba775f74cb1c (diff)
MIPS: Alchemy: RTC counter clocksource / clockevent support.
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/common/power.c')
-rw-r--r--arch/mips/alchemy/common/power.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 33a3cdb7444..997dd56bcc5 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -85,7 +85,11 @@ static unsigned int sleep_static_memctlr[4][3];
#define SLEEP_TEST_TIMEOUT 1
#ifdef SLEEP_TEST_TIMEOUT
static int sleep_ticks;
-void wakeup_counter0_set(int ticks);
+static void wakeup_counter0_set(int ticks)
+{
+ au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2);
+ au_sync();
+}
#endif
static void save_core_regs(void)
@@ -183,7 +187,6 @@ static void restore_core_regs(void)
}
restore_au1xxx_intctl();
- wakeup_counter0_adjust();
}
unsigned long suspend_mode;
@@ -411,6 +414,15 @@ static struct ctl_table pm_dir_table[] = {
*/
static int __init pm_init(void)
{
+ /* init TOY to tick at 1Hz. No need to wait for access bits
+ * since there's plenty of time between here and the first
+ * suspend cycle.
+ */
+ if (au_readl(SYS_TOYTRIM) != 32767) {
+ au_writel(32767, SYS_TOYTRIM);
+ au_sync();
+ }
+
register_sysctl_table(pm_dir_table);
return 0;
}