diff options
| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2010-04-21 17:41:59 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-04-30 20:52:43 +0100 |
| commit | 0000a5390184af1459e82506fcfa7db96f3e6d33 (patch) | |
| tree | a21be05f506bbee603e2a280d126204ce7dbf3d4 /arch/mips/alchemy | |
| parent | 0dfeecacd8e4405209f217944818b90016bb4a9d (diff) | |
MIPS: DB1200: PCMCIA card detection must not be auto-enabled.
Same issues as SD card detection: One of both is always triggering and the
handlers take care to shut it up and enable the other. To avoid messages
about "unbalanced interrupt enable/disable" they must not be automatically
enabled when initally requested.
This was not an issue with the db1200_defconfig due to fortunate timings;
on a build without network chip support the warnings appear.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1133/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
| -rw-r--r-- | arch/mips/alchemy/devboards/db1200/setup.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index be7e92ea01f..88761954755 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -66,12 +66,16 @@ static int __init db1200_arch_init(void) set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); - /* do not autoenable these: CPLD has broken edge int handling, - * and the CD handler setup requires manual enabling to work - * around that. + /* insert/eject pairs: one of both is always screaming. To avoid + * issues they must not be automatically enabled when initially + * requested. */ irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; return 0; } |