summaryrefslogtreecommitdiffstats
path: root/arch/mips/alchemy
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-03 13:28:14 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-03 13:28:14 -0700
commitd6748066ad0e8b2514545998f8367ebb3906f299 (patch)
treef7a9bfd764a8fb781aeda0ef2249afbab42dddf7 /arch/mips/alchemy
parentf04c045f8ce69c22bda9d99eb927276b776135fc (diff)
parent3ba1e543ab4b02640d396098f2f6a199560d5f2d (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits) MIPS: O32: Provide definition of registers ta0 .. ta3. MIPS: perf: Add Octeon support for hardware perf. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: Add probes for more Octeon II CPUs. MIPS: Add more CPU identifiers for Octeon II CPUs. MIPS: XLR, XLS: Add comment for smp setup MIPS: JZ4740: GPIO: Check correct IRQ in demux handler MIPS: JZ4740: GPIO: Simplify IRQ demuxer MIPS: JZ4740: Use generic irq chip MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep MIPS: Alchemy: Redo PCI as platform driver MIPS: Alchemy: more base address cleanup MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: abstract USB block control register access ... Fix up trivial conflicts in: arch/mips/alchemy/devboards/db1x00/platform.c drivers/ide/Kconfig drivers/mmc/host/au1xmmc.c drivers/video/Kconfig sound/mips/Kconfig
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/Kconfig50
-rw-r--r--arch/mips/alchemy/common/Makefile6
-rw-r--r--arch/mips/alchemy/common/dbdma.c203
-rw-r--r--arch/mips/alchemy/common/dma.c72
-rw-r--r--arch/mips/alchemy/common/gpiolib.c (renamed from arch/mips/alchemy/common/gpiolib-au1000.c)35
-rw-r--r--arch/mips/alchemy/common/pci.c104
-rw-r--r--arch/mips/alchemy/common/platform.c370
-rw-r--r--arch/mips/alchemy/common/power.c46
-rw-r--r--arch/mips/alchemy/common/setup.c6
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c153
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c28
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c198
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c49
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c190
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c33
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c71
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c6
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c119
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c12
-rw-r--r--arch/mips/alchemy/gpr/platform.c47
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c40
-rw-r--r--arch/mips/alchemy/mtx-1/platform.c62
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c8
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c12
24 files changed, 1019 insertions, 901 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2ccfd4a135b..2a68be6a1b9 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -18,20 +18,20 @@ config MIPS_MTX1
bool "4G Systems MTX-1 board"
select DMA_NONCOHERENT
select HW_HAS_PCI
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_BOSPORUS
bool "Alchemy Bosporus board"
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_DB1000
bool "Alchemy DB1000 board"
- select SOC_AU1000
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -39,14 +39,14 @@ config MIPS_DB1000
config MIPS_DB1100
bool "Alchemy DB1100 board"
- select SOC_AU1100
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_DB1200
bool "Alchemy DB1200 board"
- select SOC_AU1200
+ select ALCHEMY_GPIOINT_AU1000
select DMA_COHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -54,7 +54,7 @@ config MIPS_DB1200
config MIPS_DB1500
bool "Alchemy DB1500 board"
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
@@ -64,7 +64,7 @@ config MIPS_DB1500
config MIPS_DB1550
bool "Alchemy DB1550 board"
- select SOC_AU1550
+ select ALCHEMY_GPIOINT_AU1000
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
@@ -74,13 +74,13 @@ config MIPS_DB1550
config MIPS_MIRAGE
bool "Alchemy Mirage board"
select DMA_NONCOHERENT
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_PB1000
bool "Alchemy PB1000 board"
- select SOC_AU1000
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
@@ -89,7 +89,7 @@ config MIPS_PB1000
config MIPS_PB1100
bool "Alchemy PB1100 board"
- select SOC_AU1100
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
@@ -98,7 +98,7 @@ config MIPS_PB1100
config MIPS_PB1200
bool "Alchemy PB1200 board"
- select SOC_AU1200
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -106,7 +106,7 @@ config MIPS_PB1200
config MIPS_PB1500
bool "Alchemy PB1500 board"
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -114,7 +114,7 @@ config MIPS_PB1500
config MIPS_PB1550
bool "Alchemy PB1550 board"
- select SOC_AU1550
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
@@ -124,13 +124,13 @@ config MIPS_PB1550
config MIPS_XXS1500
bool "MyCable XXS1500 board"
select DMA_NONCOHERENT
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_GPR
bool "Trapeze ITS GPR board"
- select SOC_AU1550
+ select ALCHEMY_GPIOINT_AU1000
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
@@ -138,23 +138,3 @@ config MIPS_GPR
select SYS_HAS_EARLY_PRINTK
endchoice
-
-config SOC_AU1000
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1100
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1500
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1550
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1200
- bool
- select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 27811fe341d..811ece7b22e 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -12,9 +12,5 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
# optional gpiolib support
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
- ifeq ($(CONFIG_GPIOLIB),y)
- obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
- endif
+ obj-$(CONFIG_GPIOLIB) += gpiolib.o
endif
-
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 3a5abb54d50..0e63ee487d6 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -40,8 +40,6 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-
/*
* The Descriptor Based DMA supports up to 16 channels.
*
@@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr =
(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
static int dbdma_initialized;
-static dbdev_tab_t dbdev_tab[] = {
-#ifdef CONFIG_SOC_AU1550
+static dbdev_tab_t *dbdev_tab;
+
+static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
/* UARTS */
- { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
- { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
- { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
- { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
+ { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
+ { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
+ { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
+ { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
/* EXT DMA */
- { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
/* USB DEV */
- { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
- { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
- { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
- { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
- { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
- { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
-
- /* PSC 0 */
- { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
-
- /* PSC 1 */
- { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
-
- /* PSC 2 */
- { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
- { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
-
- /* PSC 3 */
- { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
- { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
-
- { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
- { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
+ { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
+
+ /* PSCs */
+ { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
+
+ { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
+ { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
/* MAC 0 */
- { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
/* MAC 1 */
- { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-
-#endif /* CONFIG_SOC_AU1550 */
+ { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-#ifdef CONFIG_SOC_AU1200
- { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
- { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
- { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
- { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
-
- { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+};
- { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
+ { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
+ { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
+ { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
+ { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
- { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
- { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
- { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
- { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
+ { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
- { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
+ { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
- { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
+ { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
- { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
- { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
- { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
- { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-#endif /* CONFIG_SOC_AU1200 */
+ { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-
- /* Provide 16 user definable device types */
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
+ { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
-#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
-
+/* 32 predefined plus 32 custom */
+#define DBDEV_TAB_SIZE 64
static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
@@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = {
.resume = alchemy_dbdma_resume,
};
-static int __init au1xxx_dbdma_init(void)
+static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
{
- int irq_nr, ret;
+ int ret;
+
+ dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);
+ if (!dbdev_tab)
+ return -ENOMEM;
+
+ memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
+ for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
+ dbdev_tab[ret].dev_id = ~0;
dbdma_gptr->ddma_config = 0;
dbdma_gptr->ddma_throttle = 0;
dbdma_gptr->ddma_inten = 0xffff;
au_sync();
- switch (alchemy_get_cputype()) {
- case ALCHEMY_CPU_AU1550:
- irq_nr = AU1550_DDMA_INT;
- break;
- case ALCHEMY_CPU_AU1200:
- irq_nr = AU1200_DDMA_INT;
- break;
- default:
- return -ENODEV;
- }
-
- ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
- "Au1xxx dbdma", (void *)dbdma_gptr);
+ ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",
+ (void *)dbdma_gptr);
if (ret)
printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
else {
dbdma_initialized = 1;
- printk(KERN_INFO "Alchemy DBDMA initialized\n");
register_syscore_ops(&alchemy_dbdma_syscore_ops);
}
return ret;
}
-subsys_initcall(au1xxx_dbdma_init);
-#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
+static int __init alchemy_dbdma_init(void)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1550:
+ return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
+ case ALCHEMY_CPU_AU1200:
+ return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
+ }
+ return 0;
+}
+subsys_initcall(alchemy_dbdma_init);
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 347980e79a8..9b624e2c0fc 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -40,8 +40,6 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
- defined(CONFIG_SOC_AU1100)
/*
* A note on resource allocation:
*
@@ -88,12 +86,12 @@ static const struct dma_dev {
{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
{ AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
{ AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
- { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
- { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
- { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
- { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
- { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
- { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
/* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str,
const struct dma_dev *dev;
int i, ret;
-#if defined(CONFIG_SOC_AU1100)
- if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
- return -EINVAL;
-#else
- if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
- return -EINVAL;
-#endif
+ if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
+ if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
+ return -EINVAL;
+ } else {
+ if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
+ return -EINVAL;
+ }
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
if (au1000_dma_table[i].dev_id < 0)
@@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma);
static int __init au1000_dma_init(void)
{
- int base, i;
-
- switch (alchemy_get_cputype()) {
- case ALCHEMY_CPU_AU1000:
- base = AU1000_DMA_INT_BASE;
- break;
- case ALCHEMY_CPU_AU1500:
- base = AU1500_DMA_INT_BASE;
- break;
- case ALCHEMY_CPU_AU1100:
- base = AU1100_DMA_INT_BASE;
- break;
- default:
- goto out;
- }
-
- for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
- au1000_dma_table[i].irq = base + i;
-
- printk(KERN_INFO "Alchemy DMA initialized\n");
+ int base, i;
+
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ base = AU1000_DMA_INT_BASE;
+ break;
+ case ALCHEMY_CPU_AU1500:
+ base = AU1500_DMA_INT_BASE;
+ break;
+ case ALCHEMY_CPU_AU1100:
+ base = AU1100_DMA_INT_BASE;
+ break;
+ default:
+ goto out;
+ }
+
+ for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
+ au1000_dma_table[i].irq = base + i;
+
+ printk(KERN_INFO "Alchemy DMA initialized\n");
out:
- return 0;
+ return 0;
}
arch_initcall(au1000_dma_init);
-
-#endif /* AU1000 AU1500 AU1100 */
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib.c
index c8e1a94d4a9..91fb4d9e30f 100644
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
- * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
+ * GPIOLIB support for Alchemy chips.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -23,18 +23,18 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Notes :
- * au1000 SoC have only one GPIO block : GPIO1
- * Au1100, Au15x0, Au12x0 have a second one : GPIO2
+ * This file must ONLY be built when CONFIG_GPIOLIB=y and
+ * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
+ * au1000 SoC have only one GPIO block : GPIO1
+ * Au1100, Au15x0, Au12x0 have a second one : GPIO2
*/
+#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
-#include <linux/platform_device.h>
#include <linux/gpio.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/gpio.h>
+#include <asm/mach-au1x00/gpio-au1000.h>
static int gpio2_get(struct gpio_chip *chip, unsigned offset)
{
@@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = {
},
};
-static int __init alchemy_gpiolib_init(void)
+static int __init alchemy_gpiochip_init(void)
{
- gpiochip_add(&alchemy_gpio_chip[0]);
- if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
- gpiochip_add(&alchemy_gpio_chip[1]);
-
- return 0;
+ int ret = 0;
+
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ ret = gpiochip_add(&alchemy_gpio_chip[0]);
+ break;
+ case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
+ ret = gpiochip_add(&alchemy_gpio_chip[0]);
+ ret |= gpiochip_add(&alchemy_gpio_chip[1]);
+ break;
+ }
+ return ret;
}
-arch_initcall(alchemy_gpiolib_init);
+arch_initcall(alchemy_gpiochip_init);
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
deleted file mode 100644
index 7866cf50cf9..00000000000
--- a/arch/mips/alchemy/common/pci.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Alchemy/AMD Au1x00 PCI support.
- *
- * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * Support for all devices (greater than 16) added by David Gathright.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-/* TBD */
-static struct resource pci_io_resource = {
- .start = PCI_IO_START,
- .end = PCI_IO_END,
- .name = "PCI IO space",
- .flags = IORESOURCE_IO
-};
-
-static struct resource pci_mem_resource = {
- .start = PCI_MEM_START,
- .end = PCI_MEM_END,
- .name = "PCI memory space",
- .flags = IORESOURCE_MEM
-};
-
-extern struct pci_ops au1x_pci_ops;
-
-static struct pci_controller au1x_controller = {
- .pci_ops = &au1x_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
-};
-
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-static unsigned long virt_io_addr;
-#endif
-
-static int __init au1x_pci_setup(void)
-{
- extern void au1x_pci_cfg_init(void);
-
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
- virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
- Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
-
- if (!virt_io_addr) {
- printk(KERN_ERR "Unable to ioremap pci space\n");
- return 1;
- }
- au1x_controller.io_map_base = virt_io_addr;
-
-#ifdef CONFIG_DMA_NONCOHERENT
- {
- /*
- * Set the NC bit in controller for Au1500 pre-AC silicon
- */
- u32 prid = read_c0_prid();
-
- if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
- au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
- Au1500_PCI_CFG);
- printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
- }
- }
-#endif
-
- set_io_port_base(virt_io_addr);
-#endif
-
- au1x_pci_cfg_init();
-
- register_pci_controller(&au1x_controller);
- return 0;
-}
-
-arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index f72c48d4804..c8e5d72a582 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -18,7 +18,7 @@
#include <linux/serial_8250.h>
#include <linux/slab.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
@@ -111,270 +111,87 @@ static void __init alchemy_setup_uarts(int ctype)
printk(KERN_INFO "Alchemy: failed to register UARTs\n");
}
-/* OHCI (USB full speed host controller) */
-static struct resource au1xxx_usb_ohci_resources[] = {
- [0] = {
- .start = USB_OHCI_BASE,
- .end = USB_OHCI_BASE + USB_OHCI_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = FOR_PLATFORM_C_USB_HOST_INT,
- .end = FOR_PLATFORM_C_USB_HOST_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1xxx_usb_ohci_device = {
- .name = "au1xxx-ohci",
- .id = 0,
- .dev = {
- .dma_mask = &ohci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
- .resource = au1xxx_usb_ohci_resources,
-};
-
-/*** AU1100 LCD controller ***/
-
-#ifdef CONFIG_FB_AU1100
-static struct resource au1100_lcd_resources[] = {
- [0] = {
- .start = LCD_PHYS_ADDR,
- .end = LCD_PHYS_ADDR + 0x800 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1100_LCD_INT,
- .end = AU1100_LCD_INT,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1100_lcd_device = {
- .name = "au1100-lcd",
- .id = 0,
- .dev = {
- .dma_mask = &au1100_lcd_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1100_lcd_resources),
- .resource = au1100_lcd_resources,
-};
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-/* EHCI (USB high speed host controller) */
-static struct resource au1xxx_usb_ehci_resources[] = {
- [0] = {
- .start = USB_EHCI_BASE,
- .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_USB_INT,
- .end = AU1200_USB_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1xxx_usb_ehci_device = {
- .name = "au1xxx-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
- .resource = au1xxx_usb_ehci_resources,
-};
-
-/* Au1200 UDC (USB gadget controller) */
-static struct resource au1xxx_usb_gdt_resources[] = {
- [0] = {
- .start = USB_UDC_BASE,
- .end = USB_UDC_BASE + USB_UDC_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_USB_INT,
- .end = AU1200_USB_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 udc_dmamask = DMA_BIT_MASK(32);
-static struct platform_device au1xxx_usb_gdt_device = {
- .name = "au1xxx-udc",
- .id = 0,
- .dev = {
- .dma_mask = &udc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
- .resource = au1xxx_usb_gdt_resources,
-};
+/* The dmamask must be set for OHCI/EHCI to work */
+static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
+static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
-/* Au1200 UOC (USB OTG controller) */
-static struct resource au1xxx_usb_otg_resources[] = {
- [0] = {
- .start = USB_UOC_BASE,
- .end = USB_UOC_BASE + USB_UOC_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_USB_INT,
- .end = AU1200_USB_INT,
- .flags = IORESOURCE_IRQ,
- },
+static unsigned long alchemy_ohci_data[][2] __initdata = {
+ [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
};
-static u64 uoc_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1xxx_usb_otg_device = {
- .name = "au1xxx-uoc",
- .id = 0,
- .dev = {
- .dma_mask = &uoc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
- .resource = au1xxx_usb_otg_resources,
+static unsigned long alchemy_ehci_data[][2] __initdata = {
+ [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
};
-static struct resource au1200_lcd_resources[] = {
- [0] = {
- .start = LCD_PHYS_ADDR,
- .end = LCD_PHYS_ADDR + 0x800 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_LCD_INT,
- .end = AU1200_LCD_INT,
- .flags = IORESOURCE_IRQ,
+static int __init _new_usbres(struct resource **r, struct platform_device **d)
+{
+ *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ if (!*r)
+ return -ENOMEM;
+ *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
+ if (!*d) {
+ kfree(*r);
+ return -ENOMEM;
}
-};
-
-static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1200_lcd_device = {
- .name = "au1200-lcd",
- .id = 0,
- .dev = {
- .dma_mask = &au1200_lcd_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1200_lcd_resources),
- .resource = au1200_lcd_resources,
-};
-static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
+ (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ (*d)->num_resources = 2;
+ (*d)->resource = *r;
-extern struct au1xmmc_platform_data au1xmmc_platdata[2];
+ return 0;
+}
-static struct resource au1200_mmc0_resources[] = {
- [0] = {
- .start = AU1100_SD0_PHYS_ADDR,
- .end = AU1100_SD0_PHYS_ADDR + 0xfff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_SD_INT,
- .end = AU1200_SD_INT,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = DSCR_CMD0_SDMS_TX0,
- .end = DSCR_CMD0_SDMS_TX0,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = DSCR_CMD0_SDMS_RX0,
- .end = DSCR_CMD0_SDMS_RX0,
- .flags = IORESOURCE_DMA,
- }
-};
+static void __init alchemy_setup_usb(int ctype)
+{
+ struct resource *res;
+ struct platform_device *pdev;
-static struct platform_device au1200_mmc0_device = {
- .name = "au1xxx-mmc",
- .id = 0,
- .dev = {
- .dma_mask = &au1xxx_mmc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &au1xmmc_platdata[0],
- },
- .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
- .resource = au1200_mmc0_resources,
-};
+ /* setup OHCI0. Every variant has one */
+ if (_new_usbres(&res, &pdev))
+ return;
-#ifndef CONFIG_MIPS_DB1200
-static struct resource au1200_mmc1_resources[] = {
- [0] = {
- .start = AU1100_SD1_PHYS_ADDR,
- .end = AU1100_SD1_PHYS_ADDR + 0xfff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_SD_INT,
- .end = AU1200_SD_INT,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = DSCR_CMD0_SDMS_TX1,
- .end = DSCR_CMD0_SDMS_TX1,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = DSCR_CMD0_SDMS_RX1,
- .end = DSCR_CMD0_SDMS_RX1,
- .flags = IORESOURCE_DMA,
+ res[0].start = alchemy_ohci_data[ctype][0];
+ res[0].end = res[0].start + 0x100 - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = alchemy_ohci_data[ctype][1];
+ res[1].end = res[1].start;
+ res[1].flags = IORESOURCE_IRQ;
+ pdev->name = "au1xxx-ohci";
+ pdev->id = 0;
+ pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+
+ if (platform_device_register(pdev))
+ printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
+
+
+ /* setup EHCI0: Au1200 */
+ if (ctype == ALCHEMY_CPU_AU1200) {
+ if (_new_usbres(&res, &pdev))
+ return;
+
+ res[0].start = alchemy_ehci_data[ctype][0];
+ res[0].end = res[0].start + 0x100 - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = alchemy_ehci_data[ctype][1];
+ res[1].end = res[1].start;
+ res[1].flags = IORESOURCE_IRQ;
+ pdev->name = "au1xxx-ehci";
+ pdev->id = 0;
+ pdev->dev.dma_mask = &alchemy_ehci_dmamask;
+
+ if (platform_device_register(pdev))
+ printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
}
-};
-
-static struct platform_device au1200_mmc1_device = {
- .name = "au1xxx-mmc",
- .id = 1,
- .dev = {
- .dma_mask = &au1xxx_mmc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &au1xmmc_platdata[1],
- },
- .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
- .resource = au1200_mmc1_resources,
-};
-#endif /* #ifndef CONFIG_MIPS_DB1200 */
-#endif /* #ifdef CONFIG_SOC_AU1200 */
-
-/* All Alchemy demoboards with I2C have this #define in their headers */
-#ifdef SMBUS_PSC_BASE
-static struct resource pbdb_smbus_resources[] = {
- {
- .start = CPHYSADDR(SMBUS_PSC_BASE),
- .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device pbdb_smbus_device = {
- .name = "au1xpsc_smbus",
- .id = 0, /* bus number */
- .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
- .resource = pbdb_smbus_resources,
-};
-#endif
+}
/* Macro to help defining the Ethernet MAC resources */
-#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */
-#define MAC_RES(_base, _enable, _irq) \
+#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
+#define MAC_RES(_base, _enable, _irq, _macdma) \
{ \
.start = _base, \
.end = _base + 0xffff, \
@@ -389,28 +206,37 @@ static struct platform_device pbdb_smbus_device = {
.start = _irq, \
.end = _irq, \
.flags = IORESOURCE_IRQ \
+ }, \
+ { \
+ .start = _macdma, \
+ .end = _macdma + 0x1ff, \
+ .flags = IORESOURCE_MEM, \
}
static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
[ALCHEMY_CPU_AU1000] = {
MAC_RES(AU1000_MAC0_PHYS_ADDR,
AU1000_MACEN_PHYS_ADDR,
- AU1000_MAC0_DMA_INT)
+ AU1000_MAC0_DMA_INT,
+ AU1000_MACDMA0_PHYS_ADDR)
},
[ALCHEMY_CPU_AU1500] = {
MAC_RES(AU1500_MAC0_PHYS_ADDR,
AU1500_MACEN_PHYS_ADDR,
- AU1500_MAC0_DMA_INT)
+ AU1500_MAC0_DMA_INT,
+ AU1000_MACDMA0_PHYS_ADDR)
},
[ALCHEMY_CPU_AU1100] = {
MAC_RES(AU1000_MAC0_PHYS_ADDR,
AU1000_MACEN_PHYS_ADDR,
- AU1100_MAC0_DMA_INT)
+ AU1100_MAC0_DMA_INT,
+ AU1000_MACDMA0_PHYS_ADDR)
},
[ALCHEMY_CPU_AU1550] = {
MAC_RES(AU1000_MAC0_PHYS_ADDR,
AU1000_MACEN_PHYS_ADDR,
- AU1550_MAC0_DMA_INT)
+ AU1550_MAC0_DMA_INT,
+ AU1000_MACDMA0_PHYS_ADDR)
},
};
@@ -429,17 +255,20 @@ static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
[ALCHEMY_CPU_AU1000] = {
MAC_RES(AU1000_MAC1_PHYS_ADDR,
AU1000_MACEN_PHYS_ADDR + 4,
- AU1000_MAC1_DMA_INT)
+ AU1000_MAC1_DMA_INT,
+ AU1000_MACDMA1_PHYS_ADDR)
},
[ALCHEMY_CPU_AU1500] = {
MAC_RES(AU1500_MAC1_PHYS_ADDR,
AU1500_MACEN_PHYS_ADDR + 4,
- AU1500_MAC1_DMA_INT)
+ AU1500_MAC1_DMA_INT,
+ AU1000_MACDMA1_PHYS_ADDR)
},
[ALCHEMY_CPU_AU1550] = {
MAC_RES(AU1000_MAC1_PHYS_ADDR,
AU1000_MACEN_PHYS_ADDR + 4,
- AU1550_MAC1_DMA_INT)
+ AU1550_MAC1_DMA_INT,
+ AU1000_MACDMA1_PHYS_ADDR)
},
};
@@ -521,36 +350,15 @@ static void __init alchemy_setup_macs(int ctype)
}
}
-static struct platform_device *au1xxx_platform_devices[] __initdata = {
- &au1xxx_usb_ohci_device,
-#ifdef CONFIG_FB_AU1100
- &au1100_lcd_device,
-#endif
-#ifdef CONFIG_SOC_AU1200
- &au1xxx_usb_ehci_device,
- &au1xxx_usb_gdt_device,
- &au1xxx_usb_otg_device,
- &au1200_lcd_device,
- &au1200_mmc0_device,
-#ifndef CONFIG_MIPS_DB1200
- &au1200_mmc1_device,
-#endif
-#endif
-#ifdef SMBUS_PSC_BASE
- &pbdb_smbus_device,
-#endif
-};
-
static int __init au1xxx_platform_init(void)
{
- int err, ctype = alchemy_get_cputype();
+ int ctype = alchemy_get_cputype();
alchemy_setup_uarts(ctype);
alchemy_setup_macs(ctype);
+ alchemy_setup_usb(ctype);
- err = platform_add_devices(au1xxx_platform_devices,
- ARRAY_SIZE(au1xxx_platform_devices));
- return err;
+ return 0;
}
arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index b86324a4260..bdd6651e9a4 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -37,8 +37,6 @@
#include <asm/uaccess.h>
#include <asm/mach-au1x00/au1000.h>
-#ifdef CONFIG_PM
-
/*
* We need to save/restore a bunch of core registers that are
* either volatile or reset to some state across a processor sleep.
@@ -49,7 +47,6 @@
* We only have to save/restore registers that aren't otherwise
* done as part of a driver pm_* function.
*/
-static unsigned int sleep_usb[2];
static unsigned int sleep_sys_clocks[5];
static unsigned int sleep_sys_pinfunc;
static unsigned int sleep_static_memctlr[4][3];
@@ -57,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
static void save_core_regs(void)
{
-#ifndef CONFIG_SOC_AU1200
- /* Shutdown USB host/device. */
- sleep_usb[0] = au_readl(USB_HOST_CONFIG);
-
- /* There appears to be some undocumented reset register.... */
- au_writel(0, 0xb0100004);
- au_sync();
- au_writel(0, USB_HOST_CONFIG);
- au_sync();
-
- sleep_usb[1] = au_readl(USBD_ENABLE);
- au_writel(0, USBD_ENABLE);
- au_sync();
-
-#else /* AU1200 */
-
- /* enable access to OTG mmio so we can save OTG CAP/MUX.
- * FIXME: write an OTG driver and move this stuff there!
- */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
- sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
- sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
-#endif
-
/* Clocks and PLLs. */
sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -125,22 +97,6 @@ static void restore_core_regs(void)
au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
au_sync();
-#ifndef CONFIG_SOC_AU1200
- au_writel(sleep_usb[0], USB_HOST_CONFIG);
- au_writel(sleep_usb[1], USBD_ENABLE);
- au_sync();
-#else
- /* enable access to OTG memory */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
-
- /* restore OTG caps and port mux. */
- au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
- au_sync();
- au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
- au_sync();
-#endif
-
/* Restore the static memory controller configuration. */
au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
@@ -174,5 +130,3 @@ void au_sleep(void)
restore_core_regs();
}
-
-#endif /* CONFIG_PM */
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1b887c86841..37ffd997c61 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -73,8 +73,8 @@ void __init plat_mem_setup(void)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
- u32 start = (u32)Au1500_PCI_MEM_START;
- u32 end = (u32)Au1500_PCI_MEM_END;
+ unsigned long start = ALCHEMY_PCI_MEMWIN_START;
+ unsigned long end = ALCHEMY_PCI_MEMWIN_END;
/* Don't fixup 36-bit addresses */
if ((phys_addr >> 32) != 0)
@@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
/* Check for PCI memory window */
if (phys_addr >= start && (phys_addr + size - 1) <= end)
- return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
+ return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
/* default nop */
return phys_addr;
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index dda090bf74e..c61867c93c4 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = {
.start = DB1200_IDE_INT,
.end = DB1200_IDE_INT,
.flags = IORESOURCE_IRQ,
- }
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_DMA_REQ1,
+ .end = AU1200_DSCR_CMD0_DMA_REQ1,
+ .flags = IORESOURCE_DMA,
+ },
};
static u64 ide_dmamask = DMA_BIT_MASK(32);
@@ -328,23 +333,85 @@ static struct led_classdev db1200_mmc_led = {
.brightness_set = db1200_mmcled_set,
};
-/* needed by arch/mips/alchemy/common/platform.c */
-struct au1xmmc_platform_data au1xmmc_platdata[] = {
+static struct au1xmmc_platform_data db1200mmc_platdata = {
+ .cd_setup = db1200_mmc_cd_setup,
+ .set_power = db1200_mmc_set_power,
+ .card_inserted = db1200_mmc_card_inserted,
+ .card_readonly = db1200_mmc_card_readonly,
+ .led = &db1200_mmc_led,
+};
+
+static struct resource au1200_mmc0_resources[] = {
[0] = {
- .cd_setup = db1200_mmc_cd_setup,
- .set_power = db1200_mmc_set_power,
- .card_inserted = db1200_mmc_card_inserted,
- .card_readonly = db1200_mmc_card_readonly,
- .led = &db1200_mmc_led,
+ .start = AU1100_SD0_PHYS_ADDR,
+ .end = AU1100_SD0_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_SD_INT,
+ .end = AU1200_SD_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_SDMS_TX0,
+ .end = AU1200_DSCR_CMD0_SDMS_TX0,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_SDMS_RX0,
+ .end = AU1200_DSCR_CMD0_SDMS_RX0,
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device db1200_mmc0_dev = {
+ .name = "au1xxx-mmc",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1xxx_mmc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &db1200mmc_platdata,
+ },
+ .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
+ .resource = au1200_mmc0_resources,
+};
+
+/**********************************************************************/
+
+static struct resource au1200_lcd_res[] = {
+ [0] = {
+ .start = AU1200_LCD_PHYS_ADDR,
+ .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_LCD_INT,
+ .end = AU1200_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1200_lcd_dev = {
+ .name = "au1200-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1200_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
+ .num_resources = ARRAY_SIZE(au1200_lcd_res),
+ .resource = au1200_lcd_res,
};
/**********************************************************************/
static struct resource au1200_psc0_res[] = {
[0] = {
- .start = PSC0_PHYS_ADDR,
- .end = PSC0_PHYS_ADDR + 0x000fffff,
+ .start = AU1550_PSC0_PHYS_ADDR,
+ .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -353,13 +420,13 @@ static struct resource au1200_psc0_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_PSC0_TX,
- .end = DSCR_CMD0_PSC0_TX,
+ .start = AU1200_DSCR_CMD0_PSC0_TX,
+ .end = AU1200_DSCR_CMD0_PSC0_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
- .start = DSCR_CMD0_PSC0_RX,
- .end = DSCR_CMD0_PSC0_RX,
+ .start = AU1200_DSCR_CMD0_PSC0_RX,
+ .end = AU1200_DSCR_CMD0_PSC0_RX,
.flags = IORESOURCE_DMA,
},
};
@@ -401,8 +468,8 @@ static struct platform_device db1200_spi_dev = {
static struct resource au1200_psc1_res[] = {
[0] = {
- .start = PSC1_PHYS_ADDR,
- .end = PSC1_PHYS_ADDR + 0x000fffff,
+ .start = AU1550_PSC1_PHYS_ADDR,
+ .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -411,13 +478,13 @@ static struct resource au1200_psc1_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_PSC1_TX,
- .end = DSCR_CMD0_PSC1_TX,
+ .start = AU1200_DSCR_CMD0_PSC1_TX,
+ .end = AU1200_DSCR_CMD0_PSC1_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
- .start = DSCR_CMD0_PSC1_RX,
- .end = DSCR_CMD0_PSC1_RX,
+ .start = AU1200_DSCR_CMD0_PSC1_RX,
+ .end = AU1200_DSCR_CMD0_PSC1_RX,
.flags = IORESOURCE_DMA,
},
};
@@ -449,6 +516,8 @@ static struct platform_device db1200_audiodma_dev = {
static struct platform_device *db1200_devs[] __initdata = {
NULL, /* PSC0, selected by S6.8 */
&db1200_ide_dev,
+ &db1200_mmc0_dev,
+ &au1200_lcd_dev,
&db1200_eth_dev,
&db1200_rtc_dev,
&db1200_nand_dev,
@@ -526,32 +595,28 @@ static int __init db1200_dev_init(void)
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
__raw_writel(PSC_SEL_CLK_SERCLK,
- (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+ (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb();
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- DB1200_PC0_INT,
- DB1200_PC0_INSERT_INT,
- /*DB1200_PC0_STSCHG_INT*/0,
- DB1200_PC0_EJECT_INT,
- 0);
-
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x004000000,
- PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x004000000,
- PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
- DB1200_PC1_INT,
- DB1200_PC1_INSERT_INT,
- /*DB1200_PC1_STSCHG_INT*/0,
- DB1200_PC1_EJECT_INT,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
+ /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
+
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
+ DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
+ /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
db1x_register_norflash(64 << 20, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 5c956fe8760..7cd36e631f6 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -40,24 +40,6 @@
#include <prom.h>
-#ifdef CONFIG_MIPS_DB1500
-char irq_tab_alchemy[][5] __initdata = {
- [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
- [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
-};
-
-#endif
-
-
-#ifdef CONFIG_MIPS_DB1550
-char irq_tab_alchemy[][5] __initdata = {
- [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
- [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
- [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
-};
-#endif
-
-
#ifdef CONFIG_MIPS_BOSPORUS
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
@@ -91,12 +73,6 @@ const char *get_system_type(void)
#ifdef CONFIG_MIPS_MIRAGE
-char irq_tab_alchemy[][5] __initdata = {
- [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
- [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
- [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
-};
-
static void mirage_power_off(void)
{
alchemy_gpio_direction_output(210, 1);
@@ -158,9 +134,7 @@ void __init board_setup(void)
/* initialize board register space */
bcsr_init(bcsr1, bcsr2);
- /* Not valid for Au1550 */
-#if defined(CONFIG_IRDA) && \
- (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
+#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
{
u32 pin_func;
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 7057d28f730..9e6b3d442ac 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -20,14 +20,16 @@
#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
-#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+struct pci_dev;
+
/* DB1xxx PCMCIA interrupt sources:
* CD0/1 GPIO0/3
* STSCHG0/1 GPIO1/4
@@ -88,6 +90,155 @@
#endif
#endif
+#ifdef CONFIG_PCI
+#ifdef CONFIG_MIPS_DB1500
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 12) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12)
+ return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_MIPS_DB1550
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 11) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 11)
+ return (pin == 1) ? AU1550_PCI_INTC : 0xff;
+ if (slot == 12) {
+ switch (pin) {
+ case 1: return AU1550_PCI_INTB;
+ case 2: return AU1550_PCI_INTC;
+ case 3: return AU1550_PCI_INTD;
+ case 4: return AU1550_PCI_INTA;
+ }
+ }
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1550_PCI_INTA;
+ case 2: return AU1550_PCI_INTB;
+ case 3: return AU1550_PCI_INTC;
+ case 4: return AU1550_PCI_INTD;
+ }
+ }
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_MIPS_BOSPORUS
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 11) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12)
+ return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+ if (slot == 11) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ default: return 0xff;
+ }
+ }
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_MIPS_MIRAGE
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 11) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 11)
+ return (pin == 1) ? AU1500_PCI_INTD : 0xff;
+ if (slot == 12)
+ return (pin == 3) ? AU1500_PCI_INTC : 0xff;
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ default: return 0xff;
+ }
+ }
+ return -1;
+}
+#endif
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct alchemy_pci_platdata db1xxx_pci_pd = {
+ .board_map_irq = db1xxx_map_pci_irq,
+};
+
+static struct platform_device db1xxx_pci_host_dev = {
+ .dev.platform_data = &db1xxx_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
+static int __init db15x0_pci_init(void)
+{
+ return platform_device_register(&db1xxx_pci_host_dev);
+}
+/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
+arch_initcall(db15x0_pci_init);
+#endif
+
+#ifdef CONFIG_MIPS_DB1100
+static struct resource au1100_lcd_resources[] = {
+ [0] = {
+ .start = AU1100_LCD_PHYS_ADDR,
+ .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1100_LCD_INT,
+ .end = AU1100_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1100_lcd_device = {
+ .name = "au1100-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1100_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(au1100_lcd_resources),
+ .resource = au1100_lcd_resources,
+};
+#endif
+
static struct resource alchemy_ac97c_res[] = {
[0] = {
.start = AU1000_AC97_PHYS_ADDR,
@@ -130,29 +281,28 @@ static struct platform_device db1x00_audio_dev = {
static int __init db1xxx_dev_init(void)
{
#ifdef DB1XXX_HAS_PCMCIA
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- DB1XXX_PCMCIA_CARD0,
- DB1XXX_PCMCIA_CD0,
- /*DB1XXX_PCMCIA_STSCHG0*/0,
- 0,
- 0);
-
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x004000000,
- PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x004000000,
- PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
- DB1XXX_PCMCIA_CARD1,
- DB1XXX_PCMCIA_CD1,
- /*DB1XXX_PCMCIA_STSCHG1*/0,
- 0,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
+ /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
+
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
+ DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
+ /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
+#endif
+#ifdef CONFIG_MIPS_DB1100
+ platform_device_register(&au1100_lcd_device);
#endif
db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
index 2c8dc29759f..9c57c01a68c 100644
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -19,31 +19,58 @@
*/
#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+static struct resource au1100_lcd_resources[] = {
+ [0] = {
+ .start = AU1100_LCD_PHYS_ADDR,
+ .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1100_LCD_INT,
+ .end = AU1100_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1100_lcd_device = {
+ .name = "au1100-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1100_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(au1100_lcd_resources),
+ .resource = au1100_lcd_resources,
+};
+
static int __init pb1100_dev_init(void)
{
int swapped;
/* PCMCIA. single socket, identical to Pb1500 */
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- AU1100_GPIO11_INT, /* card */
- AU1100_GPIO9_INT, /* insert */
- /*AU1100_GPIO10_INT*/0, /* stschg */
- 0, /* eject */
- 0); /* id */
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
+ /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+ platform_device_register(&au1100_lcd_device);
return 0;
}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 3ef2dceeb79..54f7f7b0676 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -24,9 +24,11 @@
#include <linux/platform_device.h>
#include <linux/smc91x.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-pb1x00/pb1200.h>
#include "../platform.h"
@@ -88,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
}
-const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
+static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
[0] = {
.set_power = pb1200mmc0_set_power,
.card_inserted = pb1200mmc0_card_inserted,
@@ -105,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
},
};
+static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
+
+static struct resource au1200_mmc0_res[] = {
+ [0] = {
+ .start = AU1100_SD0_PHYS_ADDR,
+ .end = AU1100_SD0_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_SD_INT,
+ .end = AU1200_SD_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_SDMS_TX0,
+ .end = AU1200_DSCR_CMD0_SDMS_TX0,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_SDMS_RX0,
+ .end = AU1200_DSCR_CMD0_SDMS_RX0,
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static struct platform_device pb1200_mmc0_dev = {
+ .name = "au1xxx-mmc",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1xxx_mmc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &pb1200mmc_platdata[0],
+ },
+ .num_resources = ARRAY_SIZE(au1200_mmc0_res),
+ .resource = au1200_mmc0_res,
+};
+
+static struct resource au1200_mmc1_res[] = {
+ [0] = {
+ .start = AU1100_SD1_PHYS_ADDR,
+ .end = AU1100_SD1_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_SD_INT,
+ .end = AU1200_SD_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_SDMS_TX1,
+ .end = AU1200_DSCR_CMD0_SDMS_TX1,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_SDMS_RX1,
+ .end = AU1200_DSCR_CMD0_SDMS_RX1,
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static struct platform_device pb1200_mmc1_dev = {
+ .name = "au1xxx-mmc",
+ .id = 1,
+ .dev = {
+ .dma_mask = &au1xxx_mmc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &pb1200mmc_platdata[1],
+ },
+ .num_resources = ARRAY_SIZE(au1200_mmc1_res),
+ .resource = au1200_mmc1_res,
+};
+
+
static struct resource ide_resources[] = {
[0] = {
.start = IDE_PHYS_ADDR,
@@ -115,7 +190,12 @@ static struct resource ide_resources[] = {
.start = IDE_INT,
.end = IDE_INT,
.flags = IORESOURCE_IRQ
- }
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_DMA_REQ1,
+ .end = AU1200_DSCR_CMD0_DMA_REQ1,
+ .flags = IORESOURCE_DMA,
+ },
};
static u64 ide_dmamask = DMA_BIT_MASK(32);
@@ -161,38 +241,94 @@ static struct platform_device smc91c111_device = {
.resource = smc91c111_resources
};
+static struct resource au1200_psc0_res[] = {
+ [0] = {
+ .start = AU1550_PSC0_PHYS_ADDR,
+ .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_PSC0_INT,
+ .end = AU1200_PSC0_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_PSC0_TX,
+ .end = AU1200_DSCR_CMD0_PSC0_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_PSC0_RX,
+ .end = AU1200_DSCR_CMD0_PSC0_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct platform_device pb1200_i2c_dev = {
+ .name = "au1xpsc_smbus",
+ .id = 0, /* bus number */
+ .num_resources = ARRAY_SIZE(au1200_psc0_res),
+ .resource = au1200_psc0_res,
+};
+
+static struct resource au1200_lcd_res[] = {
+ [0] = {
+ .start = AU1200_LCD_PHYS_ADDR,
+ .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_LCD_INT,
+ .end = AU1200_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1200_lcd_dev = {
+ .name = "au1200-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1200_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(au1200_lcd_res),
+ .resource = au1200_lcd_res,
+};
+
static struct platform_device *board_platform_devices[] __initdata = {
&ide_device,
- &smc91c111_device
+ &smc91c111_device,
+ &pb1200_i2c_dev,
+ &pb1200_mmc0_dev,
+ &pb1200_mmc1_dev,
+ &au1200_lcd_dev,
};
static int __init board_register_devices(void)
{
int swapped;
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- PB1200_PC0_INT,
- PB1200_PC0_INSERT_INT,
- /*PB1200_PC0_STSCHG_INT*/0,
- PB1200_PC0_EJECT_INT,
- 0);
-
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x008000000,
- PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x008000000,
- PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
- PB1200_PC1_INT,
- PB1200_PC1_INSERT_INT,
- /*PB1200_PC1_STSCHG_INT*/0,
- PB1200_PC1_EJECT_INT,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
+ /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
+
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
+ PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
+ /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 3b4fa320696..37c1883b5ea 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -33,13 +33,6 @@
#include <prom.h>
-
-char irq_tab_alchemy[][5] __initdata = {
- [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
- [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
-};
-
-
const char *get_system_type(void)
{
return "Alchemy Pb1500";
@@ -101,20 +94,18 @@ void __init board_setup(void)
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI
- /* Setup PCI bus controller */
- au_writel(0, Au1500_PCI_CMEM);
- au_writel(0x00003fff, Au1500_CFG_BASE);
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
- au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
- au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
- au_writel(0x02a00356, Au1500_PCI_STATCMD);
- au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
- au_writel(0x00000008, Au1500_PCI_MBAR);
- au_sync();
+ {
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
+ /* Setup PCI bus controller */
+ __raw_writel(0x00003fff, base + PCI_REG_CMEM);
+ __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
+ __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
+ __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
+ __raw_writel(0x00003c04, base + PCI_REG_PARAM);
+ __raw_writel(0x00000008, base + PCI_REG_MBAR);
+ wmb();
+ }
#endif
/* Enable sys bus clock divider when IDLE state or no bus activity. */
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index d443bc7aa76..1e52a01bac0 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -18,32 +18,77 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <linux/dma-mapping.h>
#include <linux/init.h>
+#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 12) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12)
+ return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct alchemy_pci_platdata pb1500_pci_pd = {
+ .board_map_irq = pb1500_map_pci_irq,
+ .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+ PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+ PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+ 0,
+#endif
+};
+
+static struct platform_device pb1500_pci_host = {
+ .dev.platform_data = &pb1500_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
static int __init pb1500_dev_init(void)
{
int swapped;
- /* PCMCIA. single socket, identical to Pb1500 */
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- AU1500_GPIO11_INT, /* card */
- AU1500_GPIO9_INT, /* insert */
- /*AU1500_GPIO10_INT*/0, /* stschg */
- 0, /* eject */
- 0); /* id */
+ /* PCMCIA. single socket, identical to Pb1100 */
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
+ /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+ platform_device_register(&pb1500_pci_host);
return 0;
}
-device_initcall(pb1500_dev_init);
+arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b790213848b..0f62d1e3df2 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -37,12 +37,6 @@
#include <prom.h>
-
-char irq_tab_alchemy[][5] __initdata = {
- [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
- [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
-};
-
const char *get_system_type(void)
{
return "Alchemy Pb1550";
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index d7150d0f49c..a4604b8a349 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -18,14 +18,89 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <linux/dma-mapping.h>
#include <linux/init.h>
-
+#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-pb1x00/pb1550.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 12) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTB;
+ case 2: return AU1500_PCI_INTC;
+ case 3: return AU1500_PCI_INTD;
+ case 4: return AU1500_PCI_INTA;
+ }
+ }
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct alchemy_pci_platdata pb1550_pci_pd = {
+ .board_map_irq = pb1550_map_pci_irq,
+};
+
+static struct platform_device pb1550_pci_host = {
+ .dev.platform_data = &pb1550_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
+static struct resource au1550_psc2_res[] = {
+ [0] = {
+ .start = AU1550_PSC2_PHYS_ADDR,
+ .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1550_PSC2_INT,
+ .end = AU1550_PSC2_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1550_DSCR_CMD0_PSC2_TX,
+ .end = AU1550_DSCR_CMD0_PSC2_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1550_DSCR_CMD0_PSC2_RX,
+ .end = AU1550_DSCR_CMD0_PSC2_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct platform_device pb1550_i2c_dev = {
+ .name = "au1xpsc_smbus",
+ .id = 0, /* bus number */
+ .num_resources = ARRAY_SIZE(au1550_psc2_res),
+ .resource = au1550_psc2_res,
+};
+
static int __init pb1550_dev_init(void)
{
int swapped;
@@ -37,33 +112,29 @@ static int __init pb1550_dev_init(void)
* drivers are used to shared irqs and b) statuschange isn't really use-
* ful anyway.
*/
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- AU1550_GPIO201_205_INT,
- AU1550_GPIO0_INT,
- 0,
- 0,
- 0);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x008000000,
- PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x008000000,
- PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
- AU1550_GPIO201_205_INT,
- AU1550_GPIO1_INT,
- 0,
- 0,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
+ AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
+ platform_device_register(&pb1550_pci_host);
+ platform_device_register(&pb1550_i2c_dev);
return 0;
}
-device_initcall(pb1550_dev_init);
+arch_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
index 5f8f0691ed2..dea45c78fdc 100644
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -36,10 +36,6 @@
#include <prom.h>
-char irq_tab_alchemy[][5] __initdata = {
- [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
-};
-
static void gpr_reset(char *c)
{
/* switch System-LED to orange (red# and green# on) */
@@ -76,12 +72,4 @@ void __init board_setup(void)
/* Take away Reset of UMTS-card */
alchemy_gpio_direction_output(215, 1);
-
-#ifdef CONFIG_PCI
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
-#endif
}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
index 14b46629cfc..982ce85db60 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = {
}
};
+
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot == 0) && (pin == 1))
+ return AU1550_PCI_INTA;
+ else if ((slot == 0) && (pin == 2))
+ return AU1550_PCI_INTB;
+
+ return -1;
+}
+
+static struct alchemy_pci_platdata gpr_pci_pd = {
+ .board_map_irq = gpr_map_pci_irq,
+ .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+ PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+ PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+ 0,
+#endif
+};
+
+static struct platform_device gpr_pci_host_dev = {
+ .dev.platform_data = &gpr_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
static struct platform_device *gpr_devices[] __initdata = {
&gpr_wdt_device,
&gpr_mtd_device,
@@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = {
&gpr_led_devices,
};
+static int __init gpr_pci_init(void)
+{
+ return platform_device_register(&gpr_pci_host_dev);
+}
+/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
+arch_initcall(gpr_pci_init);
+
+
static int __init gpr_dev_init(void)
{
i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3ae984cf98c..851a5ab4c8f 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -38,20 +38,6 @@
#include <prom.h>
-char irq_tab_alchemy[][5] __initdata = {
- [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
- [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
- [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
- [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
- [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
- [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
- [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
- [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
-};
-
-extern int (*board_pci_idsel)(unsigned int devsel, int assert);
-int mtx1_pci_idsel(unsigned int devsel, int assert);
-
static void mtx1_reset(char *c)
{
/* Jump to the reset vector */
@@ -74,15 +60,6 @@ void __init board_setup(void)
alchemy_gpio_direction_output(204, 0);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
-#ifdef CONFIG_PCI
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
- board_pci_idsel = mtx1_pci_idsel;
-#endif
-
/* Initialize sys_pinfunc */
au_writel(SYS_PF_NI2, SYS_PINFUNC);
@@ -104,23 +81,6 @@ void __init board_setup(void)
printk(KERN_INFO "4G Systems MTX-1 Board\n");
}
-int
-mtx1_pci_idsel(unsigned int devsel, int assert)
-{
- /* This function is only necessary to support a proprietary Cardbus
- * adapter on the mtx-1 "singleboard" variant. It triggers a custom
- * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
- */
- if (assert && devsel != 0)
- /* Suppress signal to Cardbus */
- alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
- else
- alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
-
- udelay(1);
- return 1;
-}
-
static int __init mtx1_init_irq(void)
{
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 55628e390fd..cc47b6868ca 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = {
.resource = &mtx1_mtd_resource,
};
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int mtx1_pci_idsel(unsigned int devsel, int assert)
+{
+ /* This function is only necessary to support a proprietary Cardbus
+ * adapter on the mtx-1 "singleboard" variant. It triggers a custom
+ * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
+ */
+ if (assert && devsel != 0)
+ /* Suppress signal to Cardbus */
+ alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
+ else
+ alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
+
+ udelay(1);
+ return 1;
+}
+
+static const char mtx1_irqtab[][5] = {
+ [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
+ [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
+ [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
+ [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
+ [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
+ [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
+ [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
+ [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
+};
+
+static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ return mtx1_irqtab[slot][pin];
+}
+
+static struct alchemy_pci_platdata mtx1_pci_pd = {
+ .board_map_irq = mtx1_map_pci_irq,
+ .board_pci_idsel = mtx1_pci_idsel,
+ .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+ PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+ PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+ 0,
+#endif
+};
+
+static struct platform_device mtx1_pci_host = {
+ .dev.platform_data = &mtx1_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
+
static struct __initdata platform_device * mtx1_devs[] = {
+ &mtx1_pci_host,
&mtx1_gpio_leds,
&mtx1_wdt,
&mtx1_button,
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 81e57fad07a..3fa83f72e01 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -70,14 +70,6 @@ void __init board_setup(void)
/* Enable DTR (MCR bit 0) = USB power up */
__raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
wmb();
-
-#ifdef CONFIG_PCI
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
-#endif
}
static int __init xxs1500_init_irq(void)
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
index e87c45cde61..06a3a459b8a 100644
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = {
{
.name = "pcmcia-io",
.flags = IORESOURCE_MEM,
- .start = PCMCIA_IO_PHYS_ADDR,
- .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
+ .start = AU1000_PCMCIA_IO_PHYS_ADDR,
+ .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
},
{
.name = "pcmcia-attr",
.flags = IORESOURCE_MEM,
- .start = PCMCIA_ATTR_PHYS_ADDR,
- .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
},
{
.name = "pcmcia-mem",
.flags = IORESOURCE_MEM,
- .start = PCMCIA_MEM_PHYS_ADDR,
- .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
+ .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
},
};