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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-13 10:44:45 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-13 10:44:45 -0700
commit31c4ab430a448cfb13fc88779d8a870c7af9f72b (patch)
treeaec64a8204ea8f89e9743cb16253de9deea4200d /arch/mips/au1000/common/time.c
parent8b69ad0e690eb5f38c23087247a12e5fde1baeff (diff)
parentf24ae12b3eeb1b956b752d4d5907e311cfa95a1a (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Workaround for a sparse warning in include/asm-mips/mach-tx4927/ioremap.h [MIPS] Make show_code static and add __user tag [MIPS] Workaround for a sparse warning in include/asm-mips/compat.h [MIPS] Add some __user tags [MIPS] math-emu minor cleanup [MIPS] Kill CONFIG_TX4927BUG_WORKAROUND [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_FB_XPERT98 [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_SRC_CLK [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_USE32K [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1XXX_PSC_SPI [CHAR] Delete leftovers of old Alchemy UART driver
Diffstat (limited to 'arch/mips/au1000/common/time.c')
-rw-r--r--arch/mips/au1000/common/time.c29
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index fa1c62f0551..8fc29982d70 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -203,11 +203,7 @@ wakeup_counter0_set(int ticks)
/* I haven't found anyone that doesn't use a 12 MHz source clock,
* but just in case.....
*/
-#ifdef CONFIG_AU1000_SRC_CLK
-#define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
-#else
#define AU1000_SRC_CLK 12000000
-#endif
/*
* We read the real processor speed from the PLL. This is important
@@ -247,33 +243,8 @@ unsigned long cal_r4koff(void)
au_writel (0, SYS_TOYWRITE);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
-#if defined(CONFIG_AU1000_USE32K)
- {
- unsigned long start, end, count;
-
- start = au_readl(SYS_RTCREAD);
- start += 2;
- /* wait for the beginning of a new tick
- */
- while (au_readl(SYS_RTCREAD) < start);
-
- /* Start r4k counter.
- */
- write_c0_count(0);
-
- /* Wait 0.5 seconds.
- */
- end = start + (32768 / trim_divide)/2;
-
- while (end > au_readl(SYS_RTCREAD));
-
- count = read_c0_count();
- cpu_speed = count * 2;
- }
-#else
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
AU1000_SRC_CLK;
-#endif
}
else {
/* The 32KHz oscillator isn't running, so assume there