diff options
| author | Ingo Molnar <mingo@elte.hu> | 2008-10-16 16:51:32 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-10-16 16:51:32 +0200 |
| commit | 5fef06e8c8c52aa7170dbbb068aa996d83738d38 (patch) | |
| tree | f46a1eefd68863bdae57afa004e5281801a6b61e /arch/mips/include/asm/asmmacro.h | |
| parent | 0c5d1eb77a8be917b638344a22afe1398236482b (diff) | |
| parent | 278429cff8809958d25415ba0ed32b59866ab1a8 (diff) | |
Merge branch 'linus' into genirq
Diffstat (limited to 'arch/mips/include/asm/asmmacro.h')
| -rw-r--r-- | arch/mips/include/asm/asmmacro.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h new file mode 100644 index 00000000000..7a881755800 --- /dev/null +++ b/arch/mips/include/asm/asmmacro.h @@ -0,0 +1,82 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef _ASM_ASMMACRO_H +#define _ASM_ASMMACRO_H + +#include <asm/hazards.h> + +#ifdef CONFIG_32BIT +#include <asm/asmmacro-32.h> +#endif +#ifdef CONFIG_64BIT +#include <asm/asmmacro-64.h> +#endif +#ifdef CONFIG_MIPS_MT_SMTC +#include <asm/mipsmtregs.h> +#endif + +#ifdef CONFIG_MIPS_MT_SMTC + .macro local_irq_enable reg=t0 + mfc0 \reg, CP0_TCSTATUS + ori \reg, \reg, TCSTATUS_IXMT + xori \reg, \reg, TCSTATUS_IXMT + mtc0 \reg, CP0_TCSTATUS + _ehb + .endm + + .macro local_irq_disable reg=t0 + mfc0 \reg, CP0_TCSTATUS + ori \reg, \reg, TCSTATUS_IXMT + mtc0 \reg, CP0_TCSTATUS + _ehb + .endm +#else + .macro local_irq_enable reg=t0 + mfc0 \reg, CP0_STATUS + ori \reg, \reg, 1 + mtc0 \reg, CP0_STATUS + irq_enable_hazard + .endm + + .macro local_irq_disable reg=t0 + mfc0 \reg, CP0_STATUS + ori \reg, \reg, 1 + xori \reg, \reg, 1 + mtc0 \reg, CP0_STATUS + irq_disable_hazard + .endm +#endif /* CONFIG_MIPS_MT_SMTC */ + +/* + * Temporary until all gas have MT ASE support + */ + .macro DMT reg=0 + .word 0x41600bc1 | (\reg << 16) + .endm + + .macro EMT reg=0 + .word 0x41600be1 | (\reg << 16) + .endm + + .macro DVPE reg=0 + .word 0x41600001 | (\reg << 16) + .endm + + .macro EVPE reg=0 + .word 0x41600021 | (\reg << 16) + .endm + + .macro MFTR rt=0, rd=0, u=0, sel=0 + .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) + .endm + + .macro MTTR rt=0, rd=0, u=0, sel=0 + .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) + .endm + +#endif /* _ASM_ASMMACRO_H */ |