diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2010-02-04 11:31:49 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 12:53:42 +0100 |
| commit | 500c2e1fdbcc2b273bd4c695a9b8ac8196f61614 (patch) | |
| tree | f24c80f609a739beed194fd5c66abf9bc48ce0d6 /arch/mips/include/asm/barrier.h | |
| parent | e275ed5ee94b358964a0dae1c8b49f0bff260b60 (diff) | |
MIPS: Optimize spinlocks.
The current locking mechanism uses a ll/sc sequence to release a
spinlock. This is slower than a wmb() followed by a store to unlock.
The branching forward to .subsection 2 on sc failure slows down the
contended case. So we get rid of that part too.
Since we are now working on naturally aligned u16 values, we can get
rid of a masking operation as the LHU already does the right thing.
The ANDI are reversed for better scheduling on multi-issue CPUs
On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet
forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/barrier.h')
| -rw-r--r-- | arch/mips/include/asm/barrier.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index a2670a239e0..c0884f02d3a 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -168,8 +168,14 @@ #ifdef CONFIG_CPU_CAVIUM_OCTEON #define smp_mb__before_llsc() smp_wmb() +/* Cause previous writes to become visible on all CPUs as soon as possible */ +#define nudge_writes() __asm__ __volatile__(".set push\n\t" \ + ".set arch=octeon\n\t" \ + "syncw\n\t" \ + ".set pop" : : : "memory") #else #define smp_mb__before_llsc() smp_llsc_mb() +#define nudge_writes() mb() #endif #endif /* __ASM_BARRIER_H */ |