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authorAnton Vorontsov <cbouatmailru@gmail.com>2008-10-18 20:28:24 +0400
committerAnton Vorontsov <cbouatmailru@gmail.com>2008-10-18 20:28:24 +0400
commited8c3174dd227031d1f3b9fa4fbb512f8f623434 (patch)
treebac4953f8899d6600f4716c0bcde1e25e34c2591 /arch/mips/include/asm/bcache.h
parent8aef7e8f8de2d900da892085edbf14ea35fe6881 (diff)
parent0cfd81031a26717fe14380d18275f8e217571615 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/power/Makefile
Diffstat (limited to 'arch/mips/include/asm/bcache.h')
-rw-r--r--arch/mips/include/asm/bcache.h60
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/mips/include/asm/bcache.h b/arch/mips/include/asm/bcache.h
new file mode 100644
index 00000000000..0ba9d6ef76a
--- /dev/null
+++ b/arch/mips/include/asm/bcache.h
@@ -0,0 +1,60 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BCACHE_H
+#define _ASM_BCACHE_H
+
+
+/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
+ chipset implemented caches. On machines with other CPUs the CPU does the
+ cache thing itself. */
+struct bcache_ops {
+ void (*bc_enable)(void);
+ void (*bc_disable)(void);
+ void (*bc_wback_inv)(unsigned long page, unsigned long size);
+ void (*bc_inv)(unsigned long page, unsigned long size);
+};
+
+extern void indy_sc_init(void);
+
+#ifdef CONFIG_BOARD_SCACHE
+
+extern struct bcache_ops *bcops;
+
+static inline void bc_enable(void)
+{
+ bcops->bc_enable();
+}
+
+static inline void bc_disable(void)
+{
+ bcops->bc_disable();
+}
+
+static inline void bc_wback_inv(unsigned long page, unsigned long size)
+{
+ bcops->bc_wback_inv(page, size);
+}
+
+static inline void bc_inv(unsigned long page, unsigned long size)
+{
+ bcops->bc_inv(page, size);
+}
+
+#else /* !defined(CONFIG_BOARD_SCACHE) */
+
+/* Not R4000 / R4400 / R4600 / R5000. */
+
+#define bc_enable() do { } while (0)
+#define bc_disable() do { } while (0)
+#define bc_wback_inv(page, size) do { } while (0)
+#define bc_inv(page, size) do { } while (0)
+
+#endif /* !defined(CONFIG_BOARD_SCACHE) */
+
+#endif /* _ASM_BCACHE_H */