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| author | Takashi Iwai <tiwai@suse.de> | 2010-08-18 15:17:30 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2010-08-18 15:17:30 +0200 |
| commit | 6ab561c8aab2e4af535f09adbc6253f958536848 (patch) | |
| tree | 37846adb4ea106485720d113e252d71d615c23ed /arch/mips/include/asm/cpu.h | |
| parent | 4f4e8f69895c8696a4bcc751817d4b186023ac44 (diff) | |
| parent | cbaa9f60d5d5c3af10f94e0d49789d5b82341a4a (diff) | |
Merge branch 'topic/isa' into topic/misc
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index a5acda41694..b201a8f5b12 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -34,7 +34,7 @@ #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 #define PRID_COMP_CAVIUM 0x0d0000 - +#define PRID_COMP_INGENIC 0xd00000 /* * Assigned values for the product ID register. In order to detect a @@ -133,6 +133,12 @@ #define PRID_IMP_CAVIUM_CN52XX 0x0700 /* + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC + */ + +#define PRID_IMP_JZRISC 0x0200 + +/* * Definitions for 7:0 on legacy processors */ @@ -219,6 +225,7 @@ enum cpu_type_enum { CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358, + CPU_JZRISC, /* * MIPS64 class processors |