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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 12:59:30 +0100
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 10:00:22 +0100
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/include/asm/gt64120.h
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/gt64120.h')
-rw-r--r--arch/mips/include/asm/gt64120.h22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h
index 0aa44abc77f..2e72abb9440 100644
--- a/arch/mips/include/asm/gt64120.h
+++ b/arch/mips/include/asm/gt64120.h
@@ -34,7 +34,7 @@
#define GT_MULTI_OFS 0x120
-/* CPU Address Decode. */
+/* CPU Address Decode. */
#define GT_SCS10LD_OFS 0x008
#define GT_SCS10HD_OFS 0x010
#define GT_SCS32LD_OFS 0x018
@@ -106,12 +106,12 @@
#define GT_ADERR_OFS 0x470
-/* SDRAM Configuration. */
+/* SDRAM Configuration. */
#define GT_SDRAM_CFG_OFS 0x448
#define GT_SDRAM_OPMODE_OFS 0x474
#define GT_SDRAM_BM_OFS 0x478
-#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
/* SDRAM Parameters. */
#define GT_SDRAM_B0_OFS 0x44c
@@ -126,14 +126,14 @@
#define GT_DEV_B3_OFS 0x468
#define GT_DEV_BOOT_OFS 0x46c
-/* ECC. */
+/* ECC. */
#define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
#define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
#define GT_ECC_MEM 0x488 /* GT-64120A only */
#define GT_ECC_CALC 0x48c /* GT-64120A only */
#define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
-/* DMA Record. */
+/* DMA Record. */
#define GT_DMA0_CNT_OFS 0x800
#define GT_DMA1_CNT_OFS 0x804
#define GT_DMA2_CNT_OFS 0x808
@@ -156,13 +156,13 @@
#define GT_DMA2_CUR_OFS 0x878
#define GT_DMA3_CUR_OFS 0x87c
-/* DMA Channel Control. */
+/* DMA Channel Control. */
#define GT_DMA0_CTRL_OFS 0x840
#define GT_DMA1_CTRL_OFS 0x844
#define GT_DMA2_CTRL_OFS 0x848
#define GT_DMA3_CTRL_OFS 0x84c
-/* DMA Arbiter. */
+/* DMA Arbiter. */
#define GT_DMA_ARB_OFS 0x860
/* Timer/Counter. */
@@ -220,7 +220,7 @@
#define GT_PCI0_CFGADDR_OFS 0xcf8
#define GT_PCI0_CFGDATA_OFS 0xcfc
-/* Interrupts. */
+/* Interrupts. */
#define GT_INTRCAUSE_OFS 0xc18
#define GT_INTRMASK_OFS 0xc1c
@@ -547,15 +547,15 @@
#define GT_DEF_BASE 0x14000000UL
#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
-#define GT_LATTIM_MIN 6 /* Minimum lat */
+#define GT_LATTIM_MIN 6 /* Minimum lat */
/*
* The gt64120_dep.h file must define the following macros
*
* GT_READ(ofs, data_pointer)
- * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit
+ * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit
*
- * TIMER - gt64120 timer irq, temporary solution until
+ * TIMER - gt64120 timer irq, temporary solution until
* full gt64120 cascade interrupt support is in place
*/