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authorIngo Molnar <mingo@elte.hu>2011-04-19 07:55:58 +0200
committerIngo Molnar <mingo@elte.hu>2011-04-19 07:56:17 +0200
commit68d2cf25d39324c54b5e42de7915c623a0917abe (patch)
treeff1291450d7e6630bc77ec1363c3db8d74fa58b0 /arch/mips/include/asm/io.h
parent176fcc5c5f0131504a55e1e1d35389c49a9177c2 (diff)
parent5d2cd90922c778908bd0cd669e572a5b5eafd737 (diff)
Merge branch 'perf/urgent' into perf/core
Merge reason: we'll be queueing up dependent changes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips/include/asm/io.h')
-rw-r--r--arch/mips/include/asm/io.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 5b017f23e24..b04e4de5dd2 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -242,7 +242,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
* This version of ioremap ensures that the memory is marked uncachable
* on the CPU as well as honouring existing caching rules from things like
* the PCI bus. Note that there are other caches and buffers on many
- * busses. In paticular driver authors should read up on PCI writes
+ * busses. In particular driver authors should read up on PCI writes
*
* It's useful if some control registers are in such an area and
* write combining or read caching is not desirable: