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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-03 13:28:14 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-03 13:28:14 -0700 |
commit | d6748066ad0e8b2514545998f8367ebb3906f299 (patch) | |
tree | f7a9bfd764a8fb781aeda0ef2249afbab42dddf7 /arch/mips/include/asm/io.h | |
parent | f04c045f8ce69c22bda9d99eb927276b776135fc (diff) | |
parent | 3ba1e543ab4b02640d396098f2f6a199560d5f2d (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits)
MIPS: O32: Provide definition of registers ta0 .. ta3.
MIPS: perf: Add Octeon support for hardware perf.
MIPS: perf: Add support for 64-bit perf counters.
MIPS: perf: Reorganize contents of perf support files.
MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
MIPS: Add accessor macros for 64-bit performance counter registers.
MIPS: Add probes for more Octeon II CPUs.
MIPS: Add more CPU identifiers for Octeon II CPUs.
MIPS: XLR, XLS: Add comment for smp setup
MIPS: JZ4740: GPIO: Check correct IRQ in demux handler
MIPS: JZ4740: GPIO: Simplify IRQ demuxer
MIPS: JZ4740: Use generic irq chip
MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
MIPS: Alchemy: kill au1xxx.h header
MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep
MIPS: Alchemy: Redo PCI as platform driver
MIPS: Alchemy: more base address cleanup
MIPS: Alchemy: rewrite USB platform setup.
MIPS: Alchemy: abstract USB block control register access
...
Fix up trivial conflicts in:
arch/mips/alchemy/devboards/db1x00/platform.c
drivers/ide/Kconfig
drivers/mmc/host/au1xmmc.c
drivers/video/Kconfig
sound/mips/Kconfig
Diffstat (limited to 'arch/mips/include/asm/io.h')
-rw-r--r-- | arch/mips/include/asm/io.h | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index b04e4de5dd2..a58f22998a8 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -329,14 +329,10 @@ static inline void pfx##write##bwlq(type val, \ "dsrl32 %L0, %L0, 0" "\n\t" \ "dsll32 %M0, %M0, 0" "\n\t" \ "or %L0, %L0, %M0" "\n\t" \ - ".set push" "\n\t" \ - ".set noreorder" "\n\t" \ - ".set nomacro" "\n\t" \ "sd %L0, %2" "\n\t" \ - ".set pop" "\n\t" \ ".set mips0" "\n" \ : "=r" (__tmp) \ - : "0" (__val), "R" (*__mem)); \ + : "0" (__val), "m" (*__mem)); \ if (irq) \ local_irq_restore(__flags); \ } else \ @@ -359,16 +355,12 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set mips3" "\t\t# __readq" "\n\t" \ - ".set push" "\n\t" \ - ".set noreorder" "\n\t" \ - ".set nomacro" "\n\t" \ "ld %L0, %1" "\n\t" \ - ".set pop" "\n\t" \ "dsra32 %M0, %L0, 0" "\n\t" \ "sll %L0, %L0, 0" "\n\t" \ ".set mips0" "\n" \ : "=r" (__val) \ - : "R" (*__mem)); \ + : "m" (*__mem)); \ if (irq) \ local_irq_restore(__flags); \ } else { \ |