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authorDavid Woodhouse <David.Woodhouse@intel.com>2008-10-13 17:13:56 +0100
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-10-13 17:13:56 +0100
commite758936e02700ff88a0b08b722a3847b95283ef2 (patch)
tree50c919bef1b459a778b85159d5929de95b6c4a01 /arch/mips/include/asm/mach-sibyte/war.h
parent239cfbde1f5843c4a24199f117d5f67f637d72d5 (diff)
parent4480f15b3306f43bbb0310d461142b4e897ca45b (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: include/asm-x86/statfs.h
Diffstat (limited to 'arch/mips/include/asm/mach-sibyte/war.h')
-rw-r--r--arch/mips/include/asm/mach-sibyte/war.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
new file mode 100644
index 00000000000..7950ef4f032
--- /dev/null
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -0,0 +1,37 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
+#define __ASM_MIPS_MACH_SIBYTE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+
+#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
+ defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
+
+#define BCM1250_M3_WAR 1
+#define SIBYTE_1956_WAR 1
+
+#else
+
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+
+#endif
+
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */