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| author | Jiri Kosina <jkosina@suse.cz> | 2010-08-10 13:22:08 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2010-08-10 13:22:08 +0200 |
| commit | fb8231a8b139035476f2a8aaac837d0099b66dad (patch) | |
| tree | 2875806beb96ea0cdab292146767a5085721dc6a /arch/mips/include/asm/octeon | |
| parent | 426d31071ac476ea62c62656b242930c17b58c00 (diff) | |
| parent | f6cec0ae58c17522a7bc4e2f39dae19f199ab534 (diff) | |
Merge branch 'master' into for-next
Conflicts:
arch/arm/mach-omap1/board-nokia770.c
Diffstat (limited to 'arch/mips/include/asm/octeon')
| -rw-r--r-- | arch/mips/include/asm/octeon/octeon.h | 3 | ||||
| -rw-r--r-- | arch/mips/include/asm/octeon/pci-octeon.h | 13 |
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index ca6214b5ccb..917a6c413b1 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -50,6 +50,7 @@ extern void octeon_crypto_disable(struct octeon_cop2_state *state, extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); extern void octeon_init_cvmcount(void); +extern void octeon_setup_delays(void); #define OCTEON_ARGV_MAX_ARGS 64 #define OCTOEN_SERIAL_LEN 20 @@ -253,4 +254,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address) extern struct cvmx_bootinfo *octeon_bootinfo; +extern uint64_t octeon_bootloader_entry_addr; + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index 6ac5d3e3398..ece78043acf 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -15,6 +15,19 @@ #define PCI_CONFIG_SPACE_DELAY 10000 /* + * The physical memory base mapped by BAR1. 256MB at the end of the + * first 4GB. + */ +#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28)) +#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) + +/* + * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, + * place BAR1 so it is the same for both. + */ +#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) + +/* * pcibios_map_irq() is defined inside pci-octeon.c. All it does is * call the Octeon specific version pointed to by this variable. This * function needs to change for PCI or PCIe based hosts. |