diff options
| author | Jonas Gorski <jonas.gorski@gmail.com> | 2012-07-24 16:33:11 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-07-24 16:33:11 +0200 |
| commit | aaf3fedb56c95b419eda4c5392e03ad9b82c4847 (patch) | |
| tree | 85a25757c0b049af11e7306cb72c9989e81c0c98 /arch/mips/include/asm | |
| parent | 4b897d5483da5c3f3c4d52440a994aad574b62b4 (diff) | |
MIPS: BCM63XX: Add flash type detection
On BCM6358 and BCM6368 the attached flash type is exposed through a
bootstrapping register. Use it for auto detecting the flash type on
those and default to parallel flash for earlier SoCs.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/3954/
Reviewed-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 6 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h index 8dcb54108c4..354b8481ec4 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h @@ -1,6 +1,12 @@ #ifndef __BCM63XX_FLASH_H #define __BCM63XX_FLASH_H +enum { + BCM63XX_FLASH_TYPE_PARALLEL, + BCM63XX_FLASH_TYPE_SERIAL, + BCM63XX_FLASH_TYPE_NAND, +}; + int __init bcm63xx_flash_register(void); #endif /* __BCM63XX_FLASH_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 6a8df5635e7..849fd97e779 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -507,6 +507,15 @@ #define GPIO_BASEMODE_6368_MASK 0x7 /* those bits must be kept as read in gpio basemode register*/ +#define GPIO_STRAPBUS_REG 0x40 +#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) +#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) +#define STRAPBUS_6368_BOOT_SEL_MASK 0x3 +#define STRAPBUS_6368_BOOT_SEL_NAND 0 +#define STRAPBUS_6368_BOOT_SEL_SERIAL 1 +#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 + + /************************************************************************* * _REG relative to RSET_ENET *************************************************************************/ |