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authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>2013-11-14 16:12:29 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-01-22 20:19:00 +0100
commit198bb4cef13525dd9391623c514557123cc6cc31 (patch)
tree8282a9e992fe0d756857f8e2846268ae9c945e2d /arch/mips/include
parentb0d4d30026ba4e5f3c71012ec90b77084fe9825b (diff)
MIPS: Add function for flushing the TLB using the TLBINV instruction
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6136/
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mipsregs.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0558f9b429a..d9910a1e754 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -705,6 +705,19 @@ static inline int mm_insn_16bit(u16 insn)
}
/*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".word 0x42000004\n\t" /* tlbinvf */
+ ".set pop");
+}
+
+
+/*
* Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
* performance counter number encoded into bits 1 ... 5 of the instruction.