diff options
| author | John Crispin <blogic@openwrt.org> | 2012-04-12 21:21:56 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-05-21 14:31:54 +0100 |
| commit | cdb8612147b7fba751e6fa193f32b09937a7e16b (patch) | |
| tree | c395b2e3da6c0a8914adaf4bf82b38565442c89c /arch/mips/include | |
| parent | ceff2676b04943638c6f599ffe4e99efb89aa625 (diff) | |
watchdog: MIPS: lantiq: implement OF support and minor fixes
Add support for OF. We also apply the following small fixes
* reduce boiler plate by using devm_request_and_ioremap
* sane error path for the clock
* move LTQ_RST_CAUSE_WDTRST to a soc specific header file
* add a message to show that the driver loaded
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Cc: linux-watchdog@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3810/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/mach-lantiq/lantiq.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 6775d2402cd..64fbc3faad6 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -49,7 +49,6 @@ extern struct clk *clk_get_io(void); extern unsigned char ltq_boot_select(void); /* find out what caused the last cpu reset */ extern int ltq_reset_cause(void); -#define LTQ_RST_CAUSE_WDTRST 0x20 #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index b5a2acf9156..d0d40a42327 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -133,6 +133,8 @@ extern __iomem void *ltq_cgu_membase; #define LTQ_WDT_BASE_ADDR 0x1F8803F0 #define LTQ_WDT_SIZE 0x10 +#define LTQ_RST_CAUSE_WDTRST 0x20 + /* STP - serial to parallel conversion unit */ #define LTQ_STP_BASE_ADDR 0x1E100BB0 #define LTQ_STP_SIZE 0x40 |