summaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/cpu-probe.c
diff options
context:
space:
mode:
authorMaciej W. Rozycki <macro@linux-mips.org>2013-09-23 14:01:53 +0100
committerRalf Baechle <ralf@linux-mips.org>2013-10-29 21:24:48 +0100
commit7f177a52a13e3d3751b599ae2b46d3d4658985cd (patch)
tree6648ace46bdcb938c636b20f7954b87f55965177 /arch/mips/kernel/cpu-probe.c
parent33afab80f0da8d7fc9e85297c86d3c46eeb185cd (diff)
MIPS: Tell R4k SC and MC variations apart
There is no reliable way to tell R4000/R4400 SC and MC variations apart, however simple heuristic should give good results. Only the MC version supports coherent caching so we can rely on such a mode having been set for KSEG0 by the power-on firmware to reliably indicate an MC processor. SC processors reportedly hang on coherent cached memory accesses and Linux is linked to a cached load address so the firmware has to use the correct caching mode to download the kernel image in a cached mode successfully. OTOH if the firmware chooses to use either the non-coherent cached or the uncached mode for KSEG0 on an MC processor, then the SC variant will be reported, just as we currently do, so no regression here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: MIPS Mailing List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5882/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c28
1 files changed, 24 insertions, 4 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5465dc183e5..040b83de00a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -376,13 +376,33 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R4000PC";
}
} else {
+ int cca = read_c0_config() & CONF_CM_CMASK;
+ int mc;
+
+ /*
+ * SC and MC versions can't be reliably told apart,
+ * but only the latter support coherent caching
+ * modes so assume the firmware has set the KSEG0
+ * coherency attribute reasonably (if uncached, we
+ * assume SC).
+ */
+ switch (cca) {
+ case CONF_CM_CACHABLE_CE:
+ case CONF_CM_CACHABLE_COW:
+ case CONF_CM_CACHABLE_CUW:
+ mc = 1;
+ break;
+ default:
+ mc = 0;
+ break;
+ }
if ((c->processor_id & PRID_REV_MASK) >=
PRID_REV_R4400) {
- c->cputype = CPU_R4400SC;
- __cpu_name[cpu] = "R4400SC";
+ c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
+ __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
} else {
- c->cputype = CPU_R4000SC;
- __cpu_name[cpu] = "R4000SC";
+ c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
+ __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
}
}