diff options
| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-03-10 01:07:45 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-03-17 01:03:26 +0000 |
| commit | 53dc80287da43b75df2fe2658651d3c5160dad8e (patch) | |
| tree | 3c4c97534c379709cd2a1dae5b90df626349f21d /arch/mips/kernel/r4k_switch.S | |
| parent | c6a2f4679331206ef5d353fc9a6cda2fa4aef8c6 (diff) | |
[MIPS] FPU ownership management & preemption fixes
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/r4k_switch.S')
| -rw-r--r-- | arch/mips/kernel/r4k_switch.S | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index cc566cf1224..c7698fd9955 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -48,8 +48,7 @@ #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t1, CP0_STATUS - LONG_S t1, THREAD_STATUS(a0) + mfc0 t2, CP0_STATUS cpu_save_nonscratch a0 LONG_S ra, THREAD_REG31(a0) @@ -59,8 +58,8 @@ PTR_L t3, TASK_THREAD_INFO(a0) LONG_L t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t2, t0, t1 - beqz t2, 1f + and t1, t0 + beqz t1, 1f nor t1, zero, t1 and t0, t0, t1 @@ -73,10 +72,13 @@ li t1, ~ST0_CU1 and t0, t0, t1 LONG_S t0, ST_OFF(t3) + /* clear thread_struct CU1 bit */ + and t2, t1 fpu_save_double a0 t0 t1 # c0_status passed in t0 # clobbers t1 1: + LONG_S t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race |