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authorChris Dearman <chris@mips.com>2006-06-20 17:15:20 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-06-29 21:10:52 +0100
commit9318c51acd9689505850152cc98277a6d6f2d752 (patch)
tree7a8d49a377bed11ba2a45643c08af47f1222c51b /arch/mips/kernel
parentf7a849153be3b66326b52dce0d07896b56cb4cd7 (diff)
[MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 8c2c359a05f..e045aba4ebd 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -597,8 +597,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
break;
case PRID_IMP_25KF:
c->cputype = CPU_25KF;
- /* Probe for L2 cache */
- c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_34K:
c->cputype = CPU_34K;