diff options
| author | Manuel Lauss <mano@roarinelk.homelinux.net> | 2008-12-21 09:26:23 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:27 +0000 |
| commit | 0c694de12b54fa96b9555e07603f567906ce21c8 (patch) | |
| tree | c7528273c1d86069cb6e83bd2b36706f663f1eb2 /arch/mips/kernel | |
| parent | 779e7d41ad004946603da139da99ba775f74cb1c (diff) | |
MIPS: Alchemy: RTC counter clocksource / clockevent support.
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device. As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.
If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 6b3c63dd181..a7162a4484c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -96,6 +96,9 @@ int allow_au1k_wait; static void au1k_wait(void) { + if (!allow_au1k_wait) + return; + /* using the wait instruction makes CP0 counter unusable */ __asm__(" .set mips3 \n" " cache 0x14, 0(%0) \n" @@ -186,8 +189,7 @@ void __init check_wait(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: - if (allow_au1k_wait) - cpu_wait = au1k_wait; + cpu_wait = au1k_wait; break; case CPU_20KC: /* |