diff options
author | Wu Zhangjin <wuzhangjin@gmail.com> | 2009-07-02 23:26:45 +0800 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2009-09-17 20:07:47 +0200 |
commit | 85749d24bcf90440b10394312e5b1c96d1a62cdb (patch) | |
tree | e244d0d79d24e066871ae207a851d38973d57345 /arch/mips/loongson/fuloong-2e/irq.c | |
parent | 8e4971175acc910eb4258df82a6bd8f2c4e4e5b5 (diff) |
MIPS: Loongson: Split common loongson source code out
To share common loongson source code between all of the loongson-based
machines. there is a need to split it out of the fuloong-2e/ directory.
at the same time, other according tuning is needed. the machine-specific
parts are defined as macros in relative header file, pci.h, mem.h,
machine.h.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson/fuloong-2e/irq.c')
-rw-r--r-- | arch/mips/loongson/fuloong-2e/irq.c | 52 |
1 files changed, 6 insertions, 46 deletions
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c index 9585f5aa7cc..7888cf69424 100644 --- a/arch/mips/loongson/fuloong-2e/irq.c +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -7,39 +7,12 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include <linux/delay.h> #include <linux/interrupt.h> #include <asm/irq_cpu.h> #include <asm/i8259.h> #include <loongson.h> -/* - * the first level int-handler will jump here if it is a bonito irq - */ -static void bonito_irqdispatch(void) -{ - u32 int_status; - int i; - - /* workaround the IO dma problem: let cpu looping to allow DMA finish */ - int_status = BONITO_INTISR; - if (int_status & (1 << 10)) { - while (int_status & (1 << 10)) { - udelay(1); - int_status = BONITO_INTISR; - } - } - - /* Get pending sources, masked by current enables */ - int_status = BONITO_INTISR & BONITO_INTEN; - - if (int_status != 0) { - i = __ffs(int_status); - int_status &= ~(1 << i); - do_IRQ(BONITO_IRQ_BASE + i); - } -} static void i8259_irqdispatch(void) { @@ -52,10 +25,8 @@ static void i8259_irqdispatch(void) spurious_interrupt(); } -asmlinkage void plat_irq_dispatch(void) +asmlinkage void mach_irq_dispatch(unsigned int pending) { - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - if (pending & CAUSEF_IP7) do_IRQ(MIPS_CPU_IRQ_BASE + 7); else if (pending & CAUSEF_IP6) /* perf counter loverflow */ @@ -73,26 +44,15 @@ static struct irqaction cascade_irqaction = { .name = "cascade", }; -void __init arch_init_irq(void) +void __init set_irq_trigger_mode(void) { - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - local_irq_disable(); - /* most bonito irq should be level triggered */ BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | - BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; - BONITO_INTSTEER = 0; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - BONITO_INTENCLR = ~0; + BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; +} +void __init mach_init_irq(void) +{ /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt |