diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-03 08:09:57 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-03 08:09:57 -0800 |
commit | 9ddfd92909ac969758684e309e62198f549786a3 (patch) | |
tree | e5799c0bb894a98f8c8948ebb568f336233fc0db /arch/mips/math-emu/dp_simple.c | |
parent | 38dc63459f185795b24a39f3f4921a433ea9980b (diff) | |
parent | 049a31afe16e733a54f7da7fdf845034758c6ee1 (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: O32: Fix ppoll
MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
MIPS: Alchemy: Fix hang with high-frequency edge interrupts
MIPS: TXx9: Fix spi-baseclk value
MIPS: bcm63xx: Set the correct BCM3302 CPU name
MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
MIPS: Avoid potential hazard on Context register
MIPS: Octeon: Use lockless interrupt controller operations when possible.
MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
MIPS: SMTC: Avoid queing multiple reschedule IPIs
MIPS: GCMP: Avoid accessing registers when they are not present
MIPS: GIC: Random fixes and enhancements.
MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
MIPS: SPRAM: Clean up support code a little
MIPS: 1004K: Enable SPRAM support.
MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
MIPS: MTI: Fix accesses to device registers on MIPS boards
...
Diffstat (limited to 'arch/mips/math-emu/dp_simple.c')
-rw-r--r-- | arch/mips/math-emu/dp_simple.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index 1c555e6c6a9..d9ae1dbabda 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c @@ -62,8 +62,6 @@ ieee754dp ieee754dp_neg(ieee754dp x) return ieee754dp_nanxcpt(y, "neg"); } - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "neg", x); return x; } @@ -76,15 +74,12 @@ ieee754dp ieee754dp_abs(ieee754dp x) CLEARCX; FLUSHXDP; + /* Clear sign ALWAYS, irrespective of NaN */ + DPSIGN(x) = 0; + if (xc == IEEE754_CLASS_SNAN) { - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); + return ieee754dp_nanxcpt(ieee754dp_indef(), "abs"); } - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "abs", x); - - /* quick fix up */ - DPSIGN(x) = 0; return x; } |