diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-30 13:59:37 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:32:30 +0100 |
commit | c78cbf49c4edf2f9ca9e56d4b87a5d6ef08b7fed (patch) | |
tree | 44bee3daac887df59c0d69658b19c21da4e1839f /arch/mips/mips-boards/sim/sim_int.c | |
parent | b288f135872b651ebf6cd1565d0709a5e31997f7 (diff) |
Support for MIPSsim, the cycle accurate MIPS simulator.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/sim/sim_int.c')
-rw-r--r-- | arch/mips/mips-boards/sim/sim_int.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c new file mode 100644 index 00000000000..a4d0a2c0503 --- /dev/null +++ b/arch/mips/mips-boards/sim/sim_int.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <asm/mips-boards/simint.h> + + +extern void mips_cpu_irq_init(int); + +extern asmlinkage void simIRQ(void); + +asmlinkage void sim_hw0_irqdispatch(struct pt_regs *regs) +{ + do_IRQ(2, regs); +} + +void __init arch_init_irq(void) +{ + /* Now safe to set the exception vector. */ + set_except_vector(0, simIRQ); + + mips_cpu_irq_init(MIPSCPU_INT_BASE); +} |