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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2012-03-09 10:55:17 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2012-03-09 10:55:17 -0800 |
| commit | b675b3667f6729dcd1036a2a129b35445947f905 (patch) | |
| tree | 0d58791e9063d3ca2c352da6f3e7df2bdb876f9d /arch/mips/mm/c-r4k.c | |
| parent | 104a5f3cad8f2f27cadbdf0029400ecd9e17ccc0 (diff) | |
| parent | 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d (diff) | |
Merge commit 'v3.3-rc6' into next
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a79fe9aa772..4f9eb0b2303 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void) loongson2_sc_init(); return; #endif + case CPU_XLP: + /* don't need to worry about L2, fully coherent */ + return; default: if (c->isa_level == MIPS_CPU_ISA_M32R1 || |