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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-03-17 12:59:22 +0900
committerRalf Baechle <ralf@linux-mips.org>2006-03-21 13:27:47 +0000
commitde862b488e81172d4c610945efd9f3fc7f4b84a7 (patch)
tree677cde48279d65350e9dc2bb92204c2efd59b11a /arch/mips/mm/c-r4k.c
parentc6281edb1d5e307f056fff0e174f60fa6133adc5 (diff)
[MIPS] TX49XX has prefetch.
The TX49XX has the prefetch instruction. It supports only Pref_Load (hint 0). Actually changes in this patch except for Kconfig are not have any effects, I added these changes to prevent misuse of unsupported hints. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9572ed44f0d..32b7f6aeb98 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -786,6 +786,7 @@ static void __init probe_pcache(void)
c->dcache.waybit = 0;
c->options |= MIPS_CPU_CACHE_CDEX_P;
+ c->options |= MIPS_CPU_PREFETCH;
break;
case CPU_R4000PC: