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authorPaul Burton <paul.burton@imgtec.com>2014-03-03 12:08:40 +0000
committerPaul Burton <paul.burton@imgtec.com>2014-05-28 16:20:14 +0100
commite2a9e5ad719fb424ab3c30520733aa0e8fbcf1ce (patch)
treefdf4723703809f156461e58305a66817339c10c9 /arch/mips/mm/init.c
parent76ae658465c2319a63f3814b1e1e6e0664a1f542 (diff)
MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entry
This is identical to kmap_coherent apart from the cache coherency attribute used for the TLB entry, so kmap_coherent is abstracted to kmap_prot which is then called for both kmap_coherent & kmap_noncoherent. This will be used by a subsequent patch. Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/mm/init.c')
-rw-r--r--arch/mips/mm/init.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 4fc74c78265..80ff52e27b7 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -114,7 +114,7 @@ static void __init kmap_coherent_init(void)
static inline void kmap_coherent_init(void) {}
#endif
-void *kmap_coherent(struct page *page, unsigned long addr)
+static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
{
enum fixed_addresses idx;
unsigned long vaddr, flags, entrylo;
@@ -133,7 +133,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
idx += in_interrupt() ? FIX_N_COLOURS : 0;
#endif
vaddr = __fix_to_virt(FIX_CMAP_END - idx);
- pte = mk_pte(page, PAGE_KERNEL);
+ pte = mk_pte(page, prot);
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
entrylo = pte.pte_high;
#else
@@ -171,6 +171,16 @@ void *kmap_coherent(struct page *page, unsigned long addr)
return (void*) vaddr;
}
+void *kmap_coherent(struct page *page, unsigned long addr)
+{
+ return __kmap_pgprot(page, addr, PAGE_KERNEL);
+}
+
+void *kmap_noncoherent(struct page *page, unsigned long addr)
+{
+ return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
+}
+
void kunmap_coherent(void)
{
#ifndef CONFIG_MIPS_MT_SMTC