diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-02-04 15:51:26 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:30:25 +0100 |
| commit | d1e344e500cc693139a69d29122db18190916448 (patch) | |
| tree | 8501c79592d6ca06ce58a0ec34375cdb0c1ade34 /arch/mips/mm | |
| parent | 28ecca4786bd8af209ae65689faa6aeea80adba2 (diff) | |
Use hardware mechanism to deal with cache aliases in the 24K.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c08fa366b18..1466c497bea 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1011,9 +1011,17 @@ static void __init probe_pcache(void) * normally they'd suffer from aliases but magic in the hardware deals * with that for us so we don't need to take care ourselves. */ - if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) + switch (c->cputype) { if (c->dcache.waysize > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; + + case CPU_R10000: + case CPU_R12000: + break; + case CPU_24K: + if (!(read_c0_config7() & (1 << 16))) + default: + c->dcache.flags |= MIPS_CACHE_ALIASES; + } switch (c->cputype) { case CPU_20KC: |