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authorRalf Baechle <ralf@linux-mips.org>2005-08-29 16:49:55 +0000
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 19:32:12 +0100
commit7623debf267521771952870549f5c5d38c408ad1 (patch)
tree10ffd54fce353ce6d9f75b62c133252ed47d086f /arch/mips/mm
parent23bbbaf89cfb9bfd1a37385bfbb4e0cab591f454 (diff)
Handle mtc0 - tlb write hazard for VR5432.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/tlbex.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index c3c75a234f5..e8a8ffd0362 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -916,6 +916,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
case CPU_VR4131:
case CPU_VR4133:
+ case CPU_R5432:
i_nop(p);
i_nop(p);
tlbw(p);