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authorRalf Baechle <ralf@linux-mips.org>2006-10-07 19:44:33 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-10-08 02:38:28 +0100
commit937a801576f954bd030d7c4a5a94571710d87c0b (patch)
tree48d3440f765b56cf32a89b4b8193dd033d8227a8 /arch/mips/momentum/ocelot_c
parent31aa36658a123263a9a69896e348b9600e050679 (diff)
[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum/ocelot_c')
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c4
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c22
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c4
3 files changed, 15 insertions, 15 deletions
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index a5dc230520d..2fb14bb08e6 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -112,7 +112,7 @@ static void end_cpci_irq(unsigned int irq)
* Interrupt handler for interrupts coming from the FPGA chip.
* It could be built in ethernet ports etc...
*/
-void ll_cpci_irq(struct pt_regs *regs)
+void ll_cpci_irq(void)
{
unsigned int irq_src, irq_mask;
@@ -123,7 +123,7 @@ void ll_cpci_irq(struct pt_regs *regs)
/* mask for just the interrupts we want */
irq_src &= ~irq_mask;
- do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs);
+ do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
}
#define shutdown_cpci_irq disable_cpci_irq
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index 9d44ae1e156..4be7b26e30e 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -59,31 +59,31 @@ static struct irqaction cascade_mv64340 = {
no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
};
-extern void ll_uart_irq(struct pt_regs *regs);
-extern void ll_cpci_irq(struct pt_regs *regs);
+extern void ll_uart_irq(void);
+extern void ll_cpci_irq(void);
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status();
if (pending & STATUSF_IP0)
- do_IRQ(0, regs);
+ do_IRQ(0);
else if (pending & STATUSF_IP1)
- do_IRQ(1, regs);
+ do_IRQ(1);
else if (pending & STATUSF_IP2)
- do_IRQ(2, regs);
+ do_IRQ(2);
else if (pending & STATUSF_IP3)
- ll_uart_irq(regs);
+ ll_uart_irq();
else if (pending & STATUSF_IP4)
- do_IRQ(4, regs);
+ do_IRQ(4);
else if (pending & STATUSF_IP5)
- ll_cpci_irq(regs);
+ ll_cpci_irq();
else if (pending & STATUSF_IP6)
ll_mv64340_irq(regs);
else if (pending & STATUSF_IP7)
- do_IRQ(7, regs);
+ do_IRQ(7);
else
- spurious_interrupt(regs);
+ spurious_interrupt();
}
void __init arch_init_irq(void)
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 9f33d8f1d82..f8efe2370ff 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -105,7 +105,7 @@ static void end_uart_irq(unsigned int irq)
/*
* Interrupt handler for interrupts coming from the FPGA chip.
*/
-void ll_uart_irq(struct pt_regs *regs)
+void ll_uart_irq(void)
{
unsigned int irq_src, irq_mask;
@@ -116,7 +116,7 @@ void ll_uart_irq(struct pt_regs *regs)
/* mask for just the interrupts we want */
irq_src &= ~irq_mask;
- do_IRQ(ls1bit8(irq_src) + 74, regs);
+ do_IRQ(ls1bit8(irq_src) + 74);
}
#define shutdown_uart_irq disable_uart_irq