diff options
| author | John Crispin <blogic@openwrt.org> | 2011-07-18 18:04:12 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-09-21 17:53:18 +0200 |
| commit | 0596954681859f1b7b7adfd58fa738c09ed2affa (patch) | |
| tree | 57deac33a10247819a049c189e41ce2bc847ce68 /arch/mips/pci | |
| parent | 77fbdb30f045084f1c65b72bd457d7406343aad7 (diff) | |
MIPS: Lantiq: Fix setting the PCI bus speed on AR9
The bits used to set the PCI bus speed on AR9 are slightly different to
those used on Danube.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2614/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-lantiq.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 603d7493e96..8656388b34b 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -171,8 +171,13 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) u32 temp_buffer; /* set clock to 33Mhz */ - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); - ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); + if (ltq_is_ar9()) { + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR); + } else { + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); + } /* external or internal clock ? */ if (conf->clock) { |