diff options
| author | Jiang Liu <jiang.liu@huawei.com> | 2012-07-24 17:20:14 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-08-23 10:11:12 -0600 |
| commit | 39a3612e03440be5e2dbd02a5672cd4d1dd243c4 (patch) | |
| tree | 34a82c4a27438b76148069ac197e6f51f023e95d /arch/mips/pci | |
| parent | 3b87011d9a84777d06b8619b69a8a6b1b4b41959 (diff) | |
MIPS: PCI: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify MIPS PCIe code.
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David Daney <david.daney@cavium.com>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-octeon.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 52a1ba70b3b..c5dfb2c87d4 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev) } /* Enable the PCIe normal error reporting */ - pos = pci_find_capability(dev, PCI_CAP_ID_EXP); - if (pos) { - /* Update Device Control */ - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); - config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ - config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ - config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ - config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); - } + config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ + config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ + config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ + config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); /* Find the Advanced Error Reporting capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |