summaryrefslogtreecommitdiffstats
path: root/arch/mips/philips/pnx8550/common
diff options
context:
space:
mode:
authorDavid Woodhouse <dwmw2@infradead.org>2007-01-18 10:34:51 +1100
committerDavid Woodhouse <dwmw2@infradead.org>2007-01-18 10:34:51 +1100
commit9cdf083f981b8d37b3212400a359368661385099 (patch)
treeaa15a6a08ad87e650dea40fb59b3180bef0d345b /arch/mips/philips/pnx8550/common
parente499e01d234a31d59679b7b1e1cf628d917ba49a (diff)
parenta8b3485287731978899ced11f24628c927890e78 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/mips/philips/pnx8550/common')
-rw-r--r--arch/mips/philips/pnx8550/common/int.c74
-rw-r--r--arch/mips/philips/pnx8550/common/prom.c20
-rw-r--r--arch/mips/philips/pnx8550/common/time.c45
3 files changed, 57 insertions, 82 deletions
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 710611615ca..2c36c108c4d 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
#include <int.h>
#include <uart.h>
-static DEFINE_SPINLOCK(irq_lock);
-
/* default prio for interrupts */
/* first one is a no-no so therefore always prio 0 (disabled) */
static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
@@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr)
}
}
-#define pnx8550_disable pnx8550_ack
-static void pnx8550_ack(unsigned int irq)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- mask_irq(irq);
- spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-#define pnx8550_enable pnx8550_unmask
-static void pnx8550_unmask(unsigned int irq)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- unmask_irq(irq);
- spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-static unsigned int startup_irq(unsigned int irq_nr)
-{
- pnx8550_unmask(irq_nr);
- return 0;
-}
-
-static void shutdown_irq(unsigned int irq_nr)
-{
- pnx8550_ack(irq_nr);
- return;
-}
-
int pnx8550_set_gic_priority(int irq, int priority)
{
int gic_irq = irq-PNX8550_INT_GIC_MIN;
@@ -192,27 +158,12 @@ int pnx8550_set_gic_priority(int irq, int priority)
return prev_priority;
}
-static inline void mask_and_ack_level_irq(unsigned int irq)
-{
- pnx8550_disable(irq);
- return;
-}
-
-static void end_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
- pnx8550_enable(irq);
- }
-}
-
static struct irq_chip level_irq_type = {
.typename = "PNX Level IRQ",
- .startup = startup_irq,
- .shutdown = shutdown_irq,
- .enable = pnx8550_enable,
- .disable = pnx8550_disable,
- .ack = mask_and_ack_level_irq,
- .end = end_irq,
+ .ack = mask_irq,
+ .mask = mask_irq,
+ .mask_ack = mask_irq,
+ .unmask = unmask_irq,
};
static struct irqaction gic_action = {
@@ -233,8 +184,8 @@ void __init arch_init_irq(void)
int configPR;
for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
- irq_desc[i].chip = &level_irq_type;
- pnx8550_ack(i); /* mask the irq just in case */
+ set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+ mask_irq(i); /* mask the irq just in case */
}
/* init of GIC/IPC interrupts */
@@ -270,7 +221,7 @@ void __init arch_init_irq(void)
/* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */
- irq_desc[i].chip = &level_irq_type;
+ set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
}
/* Priority level 0 */
@@ -279,20 +230,21 @@ void __init arch_init_irq(void)
/* Set int vector table address */
PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
- irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type;
+ set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
+ handle_level_irq);
setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
/* init of Timer interrupts */
- for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
- irq_desc[i].chip = &level_irq_type;
- }
+ for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
+ set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
/* Stop Timer 1-3 */
configPR = read_c0_config7();
configPR |= 0x00000038;
write_c0_config7(configPR);
- irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type;
+ set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
+ handle_level_irq);
setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
}
diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c
index f8952c1359c..eb6ec11fef0 100644
--- a/arch/mips/philips/pnx8550/common/prom.c
+++ b/arch/mips/philips/pnx8550/common/prom.c
@@ -35,23 +35,15 @@ char * prom_getcmdline(void)
return &(arcs_cmdline[0]);
}
-void prom_init_cmdline(void)
+void __init prom_init_cmdline(void)
{
- char *cp;
- int actr;
-
- actr = 1; /* Always ignore argv[0] */
+ int i;
- cp = &(arcs_cmdline[0]);
- while(actr < prom_argc) {
- strcpy(cp, prom_argv[actr]);
- cp += strlen(prom_argv[actr]);
- *cp++ = ' ';
- actr++;
+ arcs_cmdline[0] = '\0';
+ for (i = 0; i < prom_argc; i++) {
+ strcat(arcs_cmdline, prom_argv[i]);
+ strcat(arcs_cmdline, " ");
}
- if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
- --cp;
- *cp = '\0';
}
char *prom_getenv(char *envname)
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 65c440e8480..68def3880a1 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -33,7 +33,17 @@
#include <int.h>
#include <cm.h>
-extern unsigned int mips_hpt_frequency;
+static unsigned long cpj;
+
+static cycle_t hpt_read(void)
+{
+ return read_c0_count2();
+}
+
+static void timer_ack(void)
+{
+ write_c0_compare(cpj);
+}
/*
* pnx8550_time_init() - it does the following things:
@@ -68,27 +78,48 @@ void pnx8550_time_init(void)
* HZ timer interrupts per second.
*/
mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
+ cpj = (mips_hpt_frequency + HZ / 2) / HZ;
+ write_c0_count(0);
+ timer_ack();
+
+ /* Setup Timer 2 */
+ write_c0_count2(0);
+ write_c0_compare2(0xffffffff);
+
+ clocksource_mips.read = hpt_read;
+ mips_timer_ack = timer_ack;
+}
+
+static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
+{
+ /* Timer 2 clear interrupt */
+ write_c0_compare2(-1);
+ return IRQ_HANDLED;
}
+static struct irqaction monotonic_irqaction = {
+ .handler = monotonic_interrupt,
+ .flags = IRQF_DISABLED,
+ .name = "Monotonic timer",
+};
+
void __init plat_timer_setup(struct irqaction *irq)
{
int configPR;
setup_irq(PNX8550_INT_TIMER1, irq);
+ setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
- /* Start timer1 */
+ /* Timer 1 start */
configPR = read_c0_config7();
configPR &= ~0x00000008;
write_c0_config7(configPR);
- /* Timer 2 stop */
+ /* Timer 2 start */
configPR = read_c0_config7();
- configPR |= 0x00000010;
+ configPR &= ~0x00000010;
write_c0_config7(configPR);
- write_c0_count2(0);
- write_c0_compare2(0xffffffff);
-
/* Timer 3 stop */
configPR = read_c0_config7();
configPR |= 0x00000020;