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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-08-19 22:55:09 +0900
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 16:18:42 +0100
commitd10e025f0e4ba4b96d7b5786d232ac5b0b232b11 (patch)
treea417a55071b4b7edc22b7c5bb1a2352e7b5986d9 /arch/mips/txx9/generic/setup_tx3927.c
parent860e546c19d88c21819c7f0861c505debd2d6eed (diff)
MIPS: TXx9: Cache fixup
TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options to control them. This is useful to debug some cache-related issues, such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/generic/setup_tx3927.c')
-rw-r--r--arch/mips/txx9/generic/setup_tx3927.c18
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
index 7bd963d37fc..4bc2f859379 100644
--- a/arch/mips/txx9/generic/setup_tx3927.c
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -99,16 +99,14 @@ void __init tx3927_setup(void)
txx9_gpio_init(TX3927_PIO_REG, 0, 16);
conf = read_c0_conf();
- if (!(conf & TX39_CONF_ICE))
- printk(KERN_INFO "TX3927 I-Cache disabled.\n");
- if (!(conf & TX39_CONF_DCE))
- printk(KERN_INFO "TX3927 D-Cache disabled.\n");
- else if (!(conf & TX39_CONF_WBON))
- printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n");
- else if (!(conf & TX39_CONF_CWFON))
- printk(KERN_INFO "TX3927 D-Cache WriteBack.\n");
- else
- printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
+ if (conf & TX39_CONF_DCE) {
+ if (!(conf & TX39_CONF_WBON))
+ pr_info("TX3927 D-Cache WriteThrough.\n");
+ else if (!(conf & TX39_CONF_CWFON))
+ pr_info("TX3927 D-Cache WriteBack.\n");
+ else
+ pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
+ }
}
void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)