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author | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-06 10:37:02 -0400 |
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committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-08-06 10:37:02 -0400 |
commit | ab11b487402f97975f3ac1eeea09c82f4431481e (patch) | |
tree | 86337c5cbbd2b0c4bd07c0847a1dc7de3d898147 /arch/mips/wrppmc/pci.c | |
parent | 1c689cbcf2c2b7a35cd237abddd9206bb1b6fee1 (diff) | |
parent | fc1caf6eafb30ea185720e29f7f5eccca61ecd60 (diff) |
Merge branch 'master' into for-linus
Diffstat (limited to 'arch/mips/wrppmc/pci.c')
-rw-r--r-- | arch/mips/wrppmc/pci.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/mips/wrppmc/pci.c b/arch/mips/wrppmc/pci.c new file mode 100644 index 00000000000..d06192faeb7 --- /dev/null +++ b/arch/mips/wrppmc/pci.c @@ -0,0 +1,54 @@ +/* + * pci.c: GT64120 PCI support. + * + * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/types.h> +#include <linux/pci.h> + +#include <asm/gt64120.h> + +extern struct pci_ops gt64xxx_pci0_ops; + +static struct resource pci0_io_resource = { + .name = "pci_0 io", + .start = GT_PCI_IO_BASE, + .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct resource pci0_mem_resource = { + .name = "pci_0 memory", + .start = GT_PCI_MEM_BASE, + .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct pci_controller hose_0 = { + .pci_ops = >64xxx_pci0_ops, + .io_resource = &pci0_io_resource, + .mem_resource = &pci0_mem_resource, +}; + +static int __init gt64120_pci_init(void) +{ + u32 tmp; + + tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ + tmp = GT_READ(GT_PCI0_BARE_OFS); + + /* reset the whole PCI I/O space range */ + ioport_resource.start = GT_PCI_IO_BASE; + ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; + + register_pci_controller(&hose_0); + return 0; +} + +arch_initcall(gt64120_pci_init); |