diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 15:42:10 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 15:42:10 +0100 |
| commit | 7a5c3b8c5c27211846efe7029a3d2ee7087425e3 (patch) | |
| tree | 92530366912b64c2826a882a79ebcfbe6ec28d59 /arch/mips | |
| parent | 39b741431af7f6f46b2e0e7f7f13ea2351fb4a5f (diff) | |
| parent | 2af99920d56debcf879ac71a1934e8fcccdc713e (diff) | |
Merge branch 'next/alchemy' into mips-for-linux-next
Diffstat (limited to 'arch/mips')
78 files changed, 5259 insertions, 3738 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 2a68be6a1b9..0faaab24376 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -2,6 +2,10 @@ config ALCHEMY_GPIOINT_AU1000 bool +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 + bool + # select this in your board config if you don't want to use the gpio # namespace as documented in the manuals. In this case however you need # to create the necessary gpio_* functions in your board code/headers! @@ -22,43 +26,29 @@ config MIPS_MTX1 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_BOSPORUS - bool "Alchemy Bosporus board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_DB1000 - bool "Alchemy DB1000 board" + bool "Alchemy DB1000/DB1500/DB1100 boards" select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_DB1100 - bool "Alchemy DB1100 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK config MIPS_DB1200 - bool "Alchemy DB1200 board" + bool "Alchemy DB1200/PB1200 board" select ALCHEMY_GPIOINT_AU1000 select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_DB1500 - bool "Alchemy DB1500 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI +config MIPS_DB1300 + bool "NetLogic DB1300 board" + select ALCHEMY_GPIOINT_AU1300 + select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK @@ -66,27 +56,11 @@ config MIPS_DB1550 bool "Alchemy DB1550 board" select ALCHEMY_GPIOINT_AU1000 select HW_HAS_PCI - select DMA_NONCOHERENT + select DMA_COHERENT select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_MIRAGE - bool "Alchemy Mirage board" - select DMA_NONCOHERENT - select ALCHEMY_GPIOINT_AU1000 - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_PB1000 - bool "Alchemy PB1000 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select SWAP_IO_SPACE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_PB1100 bool "Alchemy PB1100 board" select ALCHEMY_GPIOINT_AU1000 @@ -96,14 +70,6 @@ config MIPS_PB1100 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_PB1200 - bool "Alchemy PB1200 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_PB1500 bool "Alchemy PB1500 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Makefile b/arch/mips/alchemy/Makefile new file mode 100644 index 00000000000..aac3b179bbc --- /dev/null +++ b/arch/mips/alchemy/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_MIPS_GPR) += board-gpr.o +obj-$(CONFIG_MIPS_MTX1) += board-mtx1.o +obj-$(CONFIG_MIPS_XXS1500) += board-xxs1500.o diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 96e9e41f1b2..7956274de15 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -5,62 +5,31 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/ # -# AMD Alchemy Pb1000 eval board -# -platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 -load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 - -# # AMD Alchemy Pb1100 eval board # platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 # # AMD Alchemy Pb1500 eval board # platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 # # AMD Alchemy Pb1550 eval board # platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 # -# AMD Alchemy Pb1200 eval board -# -platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 -load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 - -# -# AMD Alchemy Db1000 eval board +# AMD Alchemy Db1000/Db1500/Db1100 eval boards # platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 # -# AMD Alchemy Db1100 eval board -# -platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 - -# -# AMD Alchemy Db1500 eval board -# -platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 - -# # AMD Alchemy Db1550 eval board # platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/ @@ -68,42 +37,35 @@ cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 # -# AMD Alchemy Db1200 eval board +# AMD Alchemy Db1200/Pb1200 eval boards # platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 # -# AMD Alchemy Bosporus eval board -# -platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 - -# -# AMD Alchemy Mirage eval board +# NetLogic DBAu1300 development platform # -platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 +platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 # -# 4G-Systems eval board +# 4G-Systems MTX-1 "MeshCube" wireless router # -platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/ +platform-$(CONFIG_MIPS_MTX1) += alchemy/ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 # # MyCable eval board # -platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/ +platform-$(CONFIG_MIPS_XXS1500) += alchemy/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 # # Trapeze ITS GRP board # -platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/ +platform-$(CONFIG_MIPS_GPR) += alchemy/ load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000 # boards can specify their own <gpio.h> in one of their include dirs. diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/board-gpr.c index 982ce85db60..ba3259086b9 100644 --- a/arch/mips/alchemy/gpr/platform.c +++ b/arch/mips/alchemy/board-gpr.c @@ -1,5 +1,5 @@ /* - * GPR board platform device registration + * GPR board platform device registration (Au1550) * * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de> * @@ -18,16 +18,89 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/delay.h> #include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> #include <linux/platform_device.h> +#include <linux/pm.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/leds.h> #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> - +#include <asm/bootinfo.h> +#include <asm/reboot.h> #include <asm/mach-au1x00/au1000.h> +#include <prom.h> + +const char *get_system_type(void) +{ + return "GPR"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +} + +static void gpr_reset(char *c) +{ + /* switch System-LED to orange (red# and green# on) */ + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); + + /* trigger watchdog to reset board in 200ms */ + printk(KERN_EMERG "Triggering watchdog soft reset...\n"); + raw_local_irq_disable(); + alchemy_gpio_direction_output(1, 0); + udelay(1); + alchemy_gpio_set_value(1, 1); + while (1) + cpu_wait(); +} + +static void gpr_power_off(void) +{ + while (1) + cpu_wait(); +} + +void __init board_setup(void) +{ + printk(KERN_INFO "Trapeze ITS GPR board\n"); + + pm_power_off = gpr_power_off; + _machine_halt = gpr_power_off; + _machine_restart = gpr_reset; + + /* Enable UART1/3 */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + alchemy_uart_enable(AU1000_UART1_PHYS_ADDR); + + /* Take away Reset of UMTS-card */ + alchemy_gpio_direction_output(215, 1); +} /* * Watchdog @@ -152,7 +225,7 @@ static struct i2c_gpio_platform_data gpr_i2c_data = { .scl_is_open_drain = 1, .udelay = 2, /* ~100 kHz */ .timeout = HZ, - }; +}; static struct platform_device gpr_i2c_device = { .name = "i2c-gpio", @@ -184,7 +257,7 @@ static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) else if ((slot == 0) && (pin == 2)) return AU1550_PCI_INTB; - return -1; + return 0xff; } static struct alchemy_pci_platdata gpr_pci_pd = { diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/board-mtx1.c index cc47b6868ca..295f1a95f74 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -1,5 +1,5 @@ /* - * MTX-1 platform devices registration + * MTX-1 platform devices registration (Au1500) * * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org> * @@ -19,6 +19,8 @@ */ #include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/leds.h> #include <linux/gpio.h> @@ -27,8 +29,85 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <mtd/mtd-abi.h> - +#include <asm/bootinfo.h> +#include <asm/reboot.h> +#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1xxx_eth.h> +#include <prom.h> + +const char *get_system_type(void) +{ + return "MTX-1"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtoul(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +} + +static void mtx1_reset(char *c) +{ + /* Jump to the reset vector */ + __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); +} + +static void mtx1_power_off(void) +{ + while (1) + asm volatile ( + " .set mips32 \n" + " wait \n" + " .set mips0 \n"); +} + +void __init board_setup(void) +{ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + /* Enable USB power switch */ + alchemy_gpio_direction_output(204, 0); +#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ + + /* Initialize sys_pinfunc */ + au_writel(SYS_PF_NI2, SYS_PINFUNC); + + /* Initialize GPIO */ + au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); + alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ + alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ + alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ + alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ + + /* Enable LED and set it to green */ + alchemy_gpio_direction_output(211, 1); /* green on */ + alchemy_gpio_direction_output(212, 0); /* red off */ + + pm_power_off = mtx1_power_off; + _machine_halt = mtx1_power_off; + _machine_restart = mtx1_reset; + + printk(KERN_INFO "4G Systems MTX-1 Board\n"); +} + +/******************************************************************************/ static struct gpio_keys_button mtx1_gpio_button[] = { { @@ -195,7 +274,6 @@ static struct platform_device mtx1_pci_host = { .resource = alchemy_pci_host_res, }; - static struct __initdata platform_device * mtx1_devs[] = { &mtx1_pci_host, &mtx1_gpio_leds, @@ -206,13 +284,19 @@ static struct __initdata platform_device * mtx1_devs[] = { static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = { .phy_search_highest_addr = 1, - .phy1_search_mac0 = 1, + .phy1_search_mac0 = 1, }; static int __init mtx1_register_devices(void) { int rc; + irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); + au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata); rc = gpio_request(mtx1_gpio_button[0].gpio, @@ -226,5 +310,4 @@ static int __init mtx1_register_devices(void) out: return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); } - arch_initcall(mtx1_register_devices); diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c new file mode 100644 index 00000000000..bd551365029 --- /dev/null +++ b/arch/mips/alchemy/board-xxs1500.c @@ -0,0 +1,154 @@ +/* + * BRIEF MODULE DESCRIPTION + * MyCable XXS1500 board support + * + * Copyright 2003, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <asm/bootinfo.h> +#include <asm/reboot.h> +#include <asm/mach-au1x00/au1000.h> +#include <prom.h> + +const char *get_system_type(void) +{ + return "XXS1500"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) + memsize = 0x04000000; + + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void prom_putchar(unsigned char c) +{ + alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +} + +static void xxs1500_reset(char *c) +{ + /* Jump to the reset vector */ + __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); +} + +static void xxs1500_power_off(void) +{ + while (1) + asm volatile ( + " .set mips32 \n" + " wait \n" + " .set mips0 \n"); +} + +void __init board_setup(void) +{ + u32 pin_func; + + pm_power_off = xxs1500_power_off; + _machine_halt = xxs1500_power_off; + _machine_restart = xxs1500_reset; + + alchemy_gpio1_input_enable(); + alchemy_gpio2_enable(); + + /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ + pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; + pin_func |= SYS_PF_UR3; + au_writel(pin_func, SYS_PINFUNC); + + /* Enable UART */ + alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); + /* Enable DTR (MCR bit 0) = USB power up */ + __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); + wmb(); +} + +/******************************************************************************/ + +static struct resource xxs1500_pcmcia_res[] = { + { + .name = "pcmcia-io", + .flags = IORESOURCE_MEM, + .start = AU1000_PCMCIA_IO_PHYS_ADDR, + .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, + }, + { + .name = "pcmcia-attr", + .flags = IORESOURCE_MEM, + .start = AU1000_PCMCIA_ATTR_PHYS_ADDR, + .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + }, + { + .name = "pcmcia-mem", + .flags = IORESOURCE_MEM, + .start = AU1000_PCMCIA_MEM_PHYS_ADDR, + .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + }, +}; + +static struct platform_device xxs1500_pcmcia_dev = { + .name = "xxs1500_pcmcia", + .id = -1, + .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res), + .resource = xxs1500_pcmcia_res, +}; + +static struct platform_device *xxs1500_devs[] __initdata = { + &xxs1500_pcmcia_dev, +}; + +static int __init xxs1500_dev_init(void) +{ + irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO207_INT, IRQ_TYPE_LEVEL_LOW); + + irq_set_irq_type(AU1500_GPIO0_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO1_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO2_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(AU1500_GPIO4_INT, IRQ_TYPE_LEVEL_LOW); /* CF irq */ + irq_set_irq_type(AU1500_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); + + return platform_add_devices(xxs1500_devs, + ARRAY_SIZE(xxs1500_devs)); +} +device_initcall(xxs1500_dev_init); diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 811ece7b22e..407ebc00e66 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,9 +6,7 @@ # obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o - -obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o + sleeper.o dma.o dbdma.o vss.o irq.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 9ba407b4fc9..cf02d7dc2df 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = { { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, }; +static dbdev_tab_t au1300_dbdev_tab[] __initdata = { + { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 }, + { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 }, + { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 }, + { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +}; + /* 32 predefined plus 32 custom */ #define DBDEV_TAB_SIZE 64 @@ -1037,6 +1081,8 @@ static int __init alchemy_dbdma_init(void) return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); case ALCHEMY_CPU_AU1200: return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); + case ALCHEMY_CPU_AU1300: + return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab); } return 0; } diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c index 91fb4d9e30f..f1b50f0c01d 100644 --- a/arch/mips/alchemy/common/gpiolib.c +++ b/arch/mips/alchemy/common/gpiolib.c @@ -27,6 +27,7 @@ * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! * au1000 SoC have only one GPIO block : GPIO1 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 + * Au1300 is totally different: 1 block with up to 128 GPIOs */ #include <linux/init.h> @@ -35,6 +36,7 @@ #include <linux/types.h> #include <linux/gpio.h> #include <asm/mach-au1x00/gpio-au1000.h> +#include <asm/mach-au1x00/gpio-au1300.h> static int gpio2_get(struct gpio_chip *chip, unsigned offset) { @@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = { }, }; +static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_get_value(off + AU1300_GPIO_BASE); +} + +static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v) +{ + au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); +} + +static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); +} + +static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off, + int v) +{ + return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); +} + +static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); +} + +static struct gpio_chip au1300_gpiochip = { + .label = "alchemy-gpic", + .direction_input = alchemy_gpic_dir_input, + .direction_output = alchemy_gpic_dir_output, + .get = alchemy_gpic_get, + .set = alchemy_gpic_set, + .to_irq = alchemy_gpic_gpio_to_irq, + .base = AU1300_GPIO_BASE, + .ngpio = AU1300_GPIO_NUM, +}; + static int __init alchemy_gpiochip_init(void) { int ret = 0; @@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void) ret = gpiochip_add(&alchemy_gpio_chip[0]); ret |= gpiochip_add(&alchemy_gpio_chip[1]); break; + case ALCHEMY_CPU_AU1300: + ret = gpiochip_add(&au1300_gpiochip); + break; } return ret; } diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 8b60ba0675e..94fbcd19eb9 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -25,19 +25,15 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <linux/bitops.h> +#include <linux/export.h> #include <linux/init.h> #include <linux/interrupt.h> -#include <linux/irq.h> #include <linux/slab.h> #include <linux/syscore_ops.h> #include <asm/irq_cpu.h> -#include <asm/mipsregs.h> #include <asm/mach-au1x00/au1000.h> -#ifdef CONFIG_MIPS_PB1000 -#include <asm/mach-pb1x00/pb1000.h> -#endif +#include <asm/mach-au1x00/gpio-au1300.h> /* Interrupt Controller register offsets */ #define IC_CFG0RD 0x40 @@ -69,7 +65,17 @@ #define IC_FALLINGCLR 0x7C #define IC_TESTBIT 0x80 -static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); +/* per-processor fixed function irqs */ +struct alchemy_irqmap { + int irq; /* linux IRQ number */ + int type; /* IRQ_TYPE_ */ + int prio; /* irq priority, 0 highest, 3 lowest */ + int internal; /* GPIC: internal source (no ext. pin)? */ +}; + +static int au1x_ic_settype(struct irq_data *d, unsigned int type); +static int au1300_gpic_settype(struct irq_data *d, unsigned int type); + /* NOTE on interrupt priorities: The original writers of this code said: * @@ -77,176 +83,207 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT) * needs the highest priority. */ - -/* per-processor fixed function irqs */ -struct au1xxx_irqmap { - int im_irq; - int im_type; - int im_request; /* set 1 to get higher priority */ +struct alchemy_irqmap au1000_irqmap[] __initdata = { + { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { -1, }, }; -struct au1xxx_irqmap au1000_irqmap[] __initdata = { - { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, +struct alchemy_irqmap au1500_irqmap[] __initdata = { + { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, + { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { -1, }, }; -struct au1xxx_irqmap au1500_irqmap[] __initdata = { - { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, - { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, +struct alchemy_irqmap au1100_irqmap[] __initdata = { + { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, + { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, { -1, }, }; -struct au1xxx_irqmap au1100_irqmap[] __initdata = { - { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, - { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, +struct alchemy_irqmap au1550_irqmap[] __initdata = { + { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, + { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, + { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, + { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { -1, }, }; -struct au1xxx_irqmap au1550_irqmap[] __initdata = { - { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, - { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, +struct alchemy_irqmap au1200_irqmap[] __initdata = { + { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, + { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, + { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, + { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, { -1, }, }; -struct au1xxx_irqmap au1200_irqmap[] __initdata = { - { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { -1, }, +static struct alchemy_irqmap au1300_irqmap[] __initdata = { + /* multifunction: gpio pin or device */ + { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + /* au1300 internal */ + { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, }, + { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { -1, }, /* terminator */ }; +/******************************************************************************/ static void au1x_ic0_unmask(struct irq_data *d) { @@ -265,14 +302,6 @@ static void au1x_ic1_unmask(struct irq_data *d) __raw_writel(1 << bit, base + IC_MASKSET); __raw_writel(1 << bit, base + IC_WAKESET); - -/* very hacky. does the pb1000 cpld auto-disable this int? - * nowhere in the current kernel sources is it disabled. --mlau - */ -#if defined(CONFIG_MIPS_PB1000) - if (d->irq == AU1000_GPIO15_INT) - __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */ -#endif wmb(); } @@ -470,40 +499,219 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type) return ret; } -asmlinkage void plat_irq_dispatch(void) +/******************************************************************************/ + +/* + * au1300_gpic_chgcfg - change PIN configuration. + * @gpio: pin to change (0-based GPIO number from datasheet). + * @clr: clear all bits set in 'clr'. + * @set: set these bits. + * + * modifies a pins' configuration register, bits set in @clr will + * be cleared in the register, bits in @set will be set. + */ +static inline void au1300_gpic_chgcfg(unsigned int gpio, + unsigned long clr, + unsigned long set) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long l; + + r += gpio * 4; /* offset into pin config array */ + l = __raw_readl(r + AU1300_GPIC_PINCFG); + l &= ~clr; + l |= set; + __raw_writel(l, r + AU1300_GPIC_PINCFG); + wmb(); +} + +/* + * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl). + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to the GPIO controller, so its level can either + * be read or set through the generic GPIO functions. + * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1). + * REVISIT: is this function really necessary? + */ +void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio) +{ + au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio); + +/* + * au1300_pinfunc_to_dev - assign a pin to the device function. + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to its associated device function; the pin will be + * driven by the device and not through GPIO functions. + */ +void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + r += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, r + AU1300_GPIC_DEVSEL); + wmb(); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev); + +/* + * au1300_set_irq_priority - set internal priority of IRQ. + * @irq: irq to set priority (linux irq number). + * @p: priority (0 = highest, 3 = lowest). + */ +void au1300_set_irq_priority(unsigned int irq, int p) { - unsigned int pending = read_c0_status() & read_c0_cause(); - unsigned long s, off; - - if (pending & CAUSEF_IP7) { - off = MIPS_CPU_IRQ_BASE + 7; - goto handle; - } else if (pending & CAUSEF_IP2) { - s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT; - off = AU1000_INTC0_INT_BASE; - } else if (pending & CAUSEF_IP3) { - s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT; - off = AU1000_INTC0_INT_BASE; - } else if (pending & CAUSEF_IP4) { - s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT; - off = AU1000_INTC1_INT_BASE; - } else if (pending & CAUSEF_IP5) { - s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT; - off = AU1000_INTC1_INT_BASE; - } else - goto spurious; - - s = __raw_readl((void __iomem *)s); - if (unlikely(!s)) { -spurious: - spurious_interrupt(); - return; + irq -= ALCHEMY_GPIC_INT_BASE; + au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p)); +} +EXPORT_SYMBOL_GPL(au1300_set_irq_priority); + +/* + * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers. + * @dchan: dbdma trigger select (0, 1). + * @gpio: pin to assign as trigger. + * + * DBDMA controller has 2 external trigger sources; this function + * assigns a GPIO to the selected trigger. + */ +void au1300_set_dbdma_gpio(int dchan, unsigned int gpio) +{ + unsigned long r; + + if ((dchan >= 0) && (dchan <= 1)) { + r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + r &= ~(0xff << (8 * dchan)); + r |= (gpio & 0x7f) << (8 * dchan); + __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + wmb(); } - off += __ffs(s); -handle: - do_IRQ(off); } +static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow) +{ + au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE, + allow ? GPIC_CFG_IDLEWAKE : 0); +} + +static void au1300_gpic_mask(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_unmask(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + + gpic_pin_set_idlewake(irq, 1); + + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IEN); + wmb(); +} + +static void au1300_gpic_maskack(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */ + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_ack(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + wmb(); +} + +static struct irq_chip au1300_gpic = { + .name = "GPIOINT", + .irq_ack = au1300_gpic_ack, + .irq_mask = au1300_gpic_mask, + .irq_mask_ack = au1300_gpic_maskack, + .irq_unmask = au1300_gpic_unmask, + .irq_set_type = au1300_gpic_settype, +}; + +static int au1300_gpic_settype(struct irq_data *d, unsigned int type) +{ + unsigned long s; + unsigned char *name = NULL; + irq_flow_handler_t hdl = NULL; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + s = GPIC_CFG_IC_LEVEL_HIGH; + name = "high"; + hdl = handle_level_irq; + break; + case IRQ_TYPE_LEVEL_LOW: + s = GPIC_CFG_IC_LEVEL_LOW; + name = "low"; + hdl = handle_level_irq; + break; + case IRQ_TYPE_EDGE_RISING: + s = GPIC_CFG_IC_EDGE_RISE; + name = "posedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_FALLING: + s = GPIC_CFG_IC_EDGE_FALL; + name = "negedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_BOTH: + s = GPIC_CFG_IC_EDGE_BOTH; + name = "bothedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_NONE: + s = GPIC_CFG_IC_OFF; + name = "disabled"; + hdl = handle_level_irq; + break; + default: + return -EINVAL; + } + + __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name); + + au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s); + + return 0; +} + +/******************************************************************************/ static inline void ic_init(void __iomem *base) { @@ -521,13 +729,159 @@ static inline void ic_init(void __iomem *base) wmb(); } -static void __init au1000_init_irq(struct au1xxx_irqmap *map) +static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6]; + +static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) +{ + d[0] = __raw_readl(base + IC_CFG0RD); + d[1] = __raw_readl(base + IC_CFG1RD); + d[2] = __raw_readl(base + IC_CFG2RD); + d[3] = __raw_readl(base + IC_SRCRD); + d[4] = __raw_readl(base + IC_ASSIGNRD); + d[5] = __raw_readl(base + IC_WAKERD); + d[6] = __raw_readl(base + IC_MASKRD); + ic_init(base); /* shut it up too while at it */ +} + +static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) +{ + ic_init(base); + + __raw_writel(d[0], base + IC_CFG0SET); + __raw_writel(d[1], base + IC_CFG1SET); + __raw_writel(d[2], base + IC_CFG2SET); + __raw_writel(d[3], base + IC_SRCSET); + __raw_writel(d[4], base + IC_ASSIGNSET); + __raw_writel(d[5], base + IC_WAKESET); + wmb(); + + __raw_writel(d[6], base + IC_MASKSET); + wmb(); +} + +static int alchemy_ic_suspend(void) +{ + alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), + alchemy_gpic_pmdata); + alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), + &alchemy_gpic_pmdata[7]); + return 0; +} + +static void alchemy_ic_resume(void) +{ + alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), + &alchemy_gpic_pmdata[7]); + alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), + alchemy_gpic_pmdata); +} + +static int alchemy_gpic_suspend(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; + + /* save 4 interrupt mask status registers */ + alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); + alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); + alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); + alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); + + /* save misc register(s) */ + alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); + + /* molto silenzioso */ + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* save pin/int-type configuration */ + base += AU1300_GPIC_PINCFG; + for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++) + alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); + + wmb(); + + return 0; +} + +static void alchemy_gpic_resume(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; + + /* disable all first */ + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* restore pin/int-type configurations */ + base += AU1300_GPIC_PINCFG; + for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++) + __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2)); + wmb(); + + /* restore misc register(s) */ + base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL); + wmb(); + + /* finally restore masks */ + __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0); + __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4); + __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8); + __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc); + wmb(); +} + +static struct syscore_ops alchemy_ic_pmops = { + .suspend = alchemy_ic_suspend, + .resume = alchemy_ic_resume, +}; + +static struct syscore_ops alchemy_gpic_pmops = { + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, +}; + +/******************************************************************************/ + +/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */ +#define DISP(name, base, addr) \ +static void au1000_##name##_dispatch(unsigned int irq, struct irq_desc *d) \ +{ \ + unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \ + if (likely(r)) \ + generic_handle_irq(base + __ffs(r)); \ + else \ + spurious_interrupt(); \ +} + +DISP(ic0r0, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ0INT) +DISP(ic0r1, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ1INT) +DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT) +DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT) + +static void alchemy_gpic_dispatch(unsigned int irq, struct irq_desc *d) +{ + int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); + generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i); +} + +/******************************************************************************/ + +static void __init au1000_init_irq(struct alchemy_irqmap *map) { unsigned int bit, irq_nr; void __iomem *base; ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); + register_syscore_ops(&alchemy_ic_pmops); mips_cpu_irq_init(); /* register all 64 possible IC0+IC1 irq sources as type "none". @@ -544,8 +898,8 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) /* * Initialize IC0, which is fixed per processor. */ - while (map->im_irq != -1) { - irq_nr = map->im_irq; + while (map->irq != -1) { + irq_nr = map->irq; if (irq_nr >= AU1000_INTC1_INT_BASE) { bit = irq_nr - AU1000_INTC1_INT_BASE; @@ -554,16 +908,61 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) bit = irq_nr - AU1000_INTC0_INT_BASE; base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); } - if (map->im_request) + if (map->prio == 0) __raw_writel(1 << bit, base + IC_ASSIGNSET); - au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); + au1x_ic_settype(irq_get_irq_data(irq_nr), map->type); ++map; } - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch); +} + +static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints) +{ + int i; + void __iomem *bank_base; + + register_syscore_ops(&alchemy_gpic_pmops); + mips_cpu_irq_init(); + + /* disable & ack all possible interrupt sources */ + for (i = 0; i < 4; i++) { + bank_base = AU1300_GPIC_ADDR + (i * 4); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); + wmb(); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); + wmb(); + } + + /* register an irq_chip for them, with 2nd highest priority */ + for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { + au1300_set_irq_priority(i, 1); + au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); + } + + /* setup known on-chip sources */ + while ((i = dints->irq) != -1) { + au1300_gpic_settype(irq_get_irq_data(i), dints->type); + au1300_set_irq_priority(i, dints->prio); + + if (dints->internal) + au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); + + dints++; + } + + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch); + irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch); } +/******************************************************************************/ + void __init arch_init_irq(void) { switch (alchemy_get_cputype()) { @@ -582,65 +981,17 @@ void __init arch_init_irq(void) case ALCHEMY_CPU_AU1200: au1000_init_irq(au1200_irqmap); break; + case ALCHEMY_CPU_AU1300: + alchemy_gpic_init_irq(au1300_irqmap); + break; + default: + pr_err("unknown Alchemy IRQ core\n"); + break; } } - -static unsigned long alchemy_ic_pmdata[7 * 2]; - -static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) -{ - d[0] = __raw_readl(base + IC_CFG0RD); - d[1] = __raw_readl(base + IC_CFG1RD); - d[2] = __raw_readl(base + IC_CFG2RD); - d[3] = __raw_readl(base + IC_SRCRD); - d[4] = __raw_readl(base + IC_ASSIGNRD); - d[5] = __raw_readl(base + IC_WAKERD); - d[6] = __raw_readl(base + IC_MASKRD); - ic_init(base); /* shut it up too while at it */ -} - -static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) -{ - ic_init(base); - - __raw_writel(d[0], base + IC_CFG0SET); - __raw_writel(d[1], base + IC_CFG1SET); - __raw_writel(d[2], base + IC_CFG2SET); - __raw_writel(d[3], base + IC_SRCSET); - __raw_writel(d[4], base + IC_ASSIGNSET); - __raw_writel(d[5], base + IC_WAKESET); - wmb(); - - __raw_writel(d[6], base + IC_MASKSET); - wmb(); -} - -static int alchemy_ic_suspend(void) -{ - alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), - alchemy_ic_pmdata); - alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), - &alchemy_ic_pmdata[7]); - return 0; -} - -static void alchemy_ic_resume(void) -{ - alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), - &alchemy_ic_pmdata[7]); - alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), - alchemy_ic_pmdata); -} - -static struct syscore_ops alchemy_ic_syscore_ops = { - .suspend = alchemy_ic_suspend, - .resume = alchemy_ic_resume, -}; - -static int __init alchemy_ic_pm_init(void) +asmlinkage void plat_irq_dispatch(void) { - register_syscore_ops(&alchemy_ic_syscore_ops); - return 0; + unsigned long r = (read_c0_status() & read_c0_cause()) >> 8; + do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff)); } -device_initcall(alchemy_ic_pm_init); diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index c8e5d72a582..95cb9113b12 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = { PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), }, + [ALCHEMY_CPU_AU1300] = { + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), + }, }; static struct platform_device au1xx0_uart_device = { @@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = { [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, + [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT }, }; static unsigned long alchemy_ehci_data[][2] __initdata = { [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, + [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT }, }; static int __init _new_usbres(struct resource **r, struct platform_device **d) @@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype) printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); - /* setup EHCI0: Au1200 */ - if (ctype == ALCHEMY_CPU_AU1200) { + /* setup EHCI0: Au1200/Au1300 */ + if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) { if (_new_usbres(&res, &pdev)) return; @@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype) if (platform_device_register(pdev)) printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); } + + /* Au1300: OHCI1 */ + if (ctype == ALCHEMY_CPU_AU1300) { + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = AU1300_USB_OHCI1_PHYS_ADDR; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = AU1300_USB_INT; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ohci"; + pdev->id = 1; + pdev->dev.dma_mask = &alchemy_ohci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n"); + } } /* Macro to help defining the Ethernet MAC resources */ diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index bdd6651e9a4..0c7fce2a3c1 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -126,6 +126,9 @@ void au_sleep(void) case ALCHEMY_CPU_AU1200: alchemy_sleep_au1550(); break; + case ALCHEMY_CPU_AU1300: + alchemy_sleep_au1300(); + break; } restore_core_regs(); diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index 77f3c743b71..c7bcc7e5c82 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S @@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550) END(alchemy_sleep_au1550) +/* sleepcode for Au1300 memory controller type */ +LEAF(alchemy_sleep_au1300) + + SETUP_SLEEP + + /* cache following instructions, as memory gets put to sleep */ + la t0, 2f + la t1, 4f + subu t2, t1, t0 + + .set mips3 + +1: cache 0x14, 0(t0) + subu t2, t2, 32 + bgez t2, 1b + addu t0, t0, 32 + + .set mips0 + +2: lui a0, 0xb400 /* mem_xxx */ + + /* disable all ports in mem_sdportcfga */ + sw zero, 0x868(a0) /* mem_sdportcfga */ + sync + + /* disable ODT */ + li t0, 0x03010000 + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sync + + /* precharge */ + li t0, 0x23000400 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* auto refresh */ + sw zero, 0x08c8(a0) /* mem_sdautoref */ + sync + + /* block access to the DDR */ + lw t0, 0x0848(a0) /* mem_sdconfigb */ + li t1, (1 << 7 | 0x3F) + or t0, t0, t1 + sw t0, 0x0848(a0) /* mem_sdconfigb */ + sync + + /* issue the Self Refresh command */ + li t0, 0x10000000 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* wait for sdram to enter self-refresh mode */ + lui t0, 0x0300 +3: lw t1, 0x0850(a0) /* mem_sdstat */ + and t2, t1, t0 + bne t2, t0, 3b + nop + + /* disable SDRAM clocks */ + li t0, ~(3<<28) + lw t1, 0x0840(a0) /* mem_sdconfiga */ + and t1, t1, t0 /* clear CE[1:0] */ + sw t1, 0x0840(a0) /* mem_sdconfiga */ + sync + + DO_SLEEP +4: + +END(alchemy_sleep_au1300) + /* This is where we return upon wakeup. * Reload all of the registers and return. diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 146a5fa8036..7da4d008148 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = { AU1100_RTC_MATCH2_INT, AU1550_RTC_MATCH2_INT, AU1200_RTC_MATCH2_INT, + AU1300_RTC_MATCH2_INT, }; void __init plat_time_init(void) diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c new file mode 100644 index 00000000000..d23b1444d36 --- /dev/null +++ b/arch/mips/alchemy/common/vss.c @@ -0,0 +1,84 @@ +/* + * Au1300 media block power gating (VSS) + * + * This is a stop-gap solution until I have the clock framework integration + * ready. This stuff here really must be handled transparently when clocks + * for various media blocks are enabled/disabled. + */ + +#include <linux/module.h> +#include <linux/spinlock.h> +#include <asm/mach-au1x00/au1000.h> + +#define VSS_GATE 0x00 /* gate wait timers */ +#define VSS_CLKRST 0x04 /* clock/block control */ +#define VSS_FTR 0x08 /* footers */ + +#define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c)) + +static DEFINE_SPINLOCK(au1300_vss_lock); + +/* enable a block as outlined in the databook */ +static inline void __enable_block(int block) +{ + void __iomem *base = (void __iomem *)VSS_ADDR(block); + + __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ + wmb(); + + __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ + wmb(); + + /* enable footers in sequence */ + __raw_writel(0x01, base + VSS_FTR); + wmb(); + __raw_writel(0x03, base + VSS_FTR); + wmb(); + __raw_writel(0x07, base + VSS_FTR); + wmb(); + __raw_writel(0x0f, base + VSS_FTR); + wmb(); + + __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ + wmb(); + + __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ + wmb(); + + __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ + wmb(); +} + +/* disable a block as outlined in the databook */ +static inline void __disable_block(int block) +{ + void __iomem *base = (void __iomem *)VSS_ADDR(block); + + __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ + wmb(); + __raw_writel(0, base + VSS_GATE); /* disable FSM */ + wmb(); + __raw_writel(3, base + VSS_CLKRST); /* assert reset */ + wmb(); + __raw_writel(1, base + VSS_CLKRST); /* disable clock */ + wmb(); + __raw_writel(0, base + VSS_FTR); /* disable all footers */ + wmb(); +} + +void au1300_vss_block_control(int block, int enable) +{ + unsigned long flags; + + if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300) + return; + + /* only one block at a time */ + spin_lock_irqsave(&au1300_vss_lock, flags); + if (enable) + __enable_block(block); + else + __disable_block(block); + spin_unlock_irqrestore(&au1300_vss_lock, flags); +} +EXPORT_SYMBOL_GPL(au1300_vss_block_control); diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 826449c817c..3c37fb30336 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -4,15 +4,10 @@ obj-y += prom.o bcsr.o platform.o obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_MIPS_PB1000) += pb1000/ -obj-$(CONFIG_MIPS_PB1100) += pb1100/ -obj-$(CONFIG_MIPS_PB1200) += pb1200/ -obj-$(CONFIG_MIPS_PB1500) += pb1500/ -obj-$(CONFIG_MIPS_PB1550) += pb1550/ -obj-$(CONFIG_MIPS_DB1000) += db1x00/ -obj-$(CONFIG_MIPS_DB1100) += db1x00/ -obj-$(CONFIG_MIPS_DB1200) += db1200/ -obj-$(CONFIG_MIPS_DB1500) += db1x00/ -obj-$(CONFIG_MIPS_DB1550) += db1x00/ -obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ -obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ +obj-$(CONFIG_MIPS_PB1100) += pb1100.o +obj-$(CONFIG_MIPS_PB1500) += pb1500.o +obj-$(CONFIG_MIPS_PB1550) += pb1550.o +obj-$(CONFIG_MIPS_DB1000) += db1000.o +obj-$(CONFIG_MIPS_DB1200) += db1200.o +obj-$(CONFIG_MIPS_DB1300) += db1300.o +obj-$(CONFIG_MIPS_DB1550) += db1550.o diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index 463d2c4d944..1e83ce2e114 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c @@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) enable_irq(irq); } -/* NOTE: both the enable and mask bits must be cleared, otherwise the - * CPLD generates tons of spurious interrupts (at least on my DB1200). - * -- mlau - */ static void bcsr_irq_mask(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); wmb(); } @@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d) static void bcsr_irq_maskack(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ wmb(); @@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d) static void bcsr_irq_unmask(struct irq_data *d) { unsigned short v = 1 << (d->irq - bcsr_csc_base); - __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); wmb(); } @@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) { unsigned int irq; - /* mask & disable & ack all */ - __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR); + /* mask & enable & ack all */ __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); + __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET); __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); wmb(); diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c new file mode 100644 index 00000000000..1b81dbf6b80 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1000.c @@ -0,0 +1,565 @@ +/* + * DBAu1000/1500/1100 board support + * + * Copyright 2000, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/dma-mapping.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/leds.h> +#include <linux/mmc/host.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/spi/ads7846.h> +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1000_dma.h> +#include <asm/mach-au1x00/au1100_mmc.h> +#include <asm/mach-db1x00/bcsr.h> +#include <asm/reboot.h> +#include <prom.h> +#include "platform.h" + +#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) + +struct pci_dev; + +static const char *board_type_str(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_DB1000: + return "DB1000"; + case BCSR_WHOAMI_DB1500: + return "DB1500"; + case BCSR_WHOAMI_DB1100: + return "DB1100"; + default: + return "(unknown)"; + } +} + +const char *get_system_type(void) +{ + return board_type_str(); +} + +void __init board_setup(void) +{ + /* initialize board register space */ + bcsr_init(DB1000_BCSR_PHYS_ADDR, + DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); + + printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str()); +} + + +static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1500_pci_pd = { + .board_map_irq = db1500_map_pci_irq, +}; + +static struct platform_device db1500_pci_host_dev = { + .dev.platform_data = &db1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init db1500_pci_init(void) +{ + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500) + return platform_device_register(&db1500_pci_host_dev); + return 0; +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(db1500_pci_init); + + +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; + +static struct resource alchemy_ac97c_res[] = { + [0] = { + .start = AU1000_AC97_PHYS_ADDR, + .end = AU1000_AC97_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMA_ID_AC97C_TX, + .end = DMA_ID_AC97C_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMA_ID_AC97C_RX, + .end = DMA_ID_AC97C_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device alchemy_ac97c_dev = { + .name = "alchemy-ac97c", + .id = -1, + .resource = alchemy_ac97c_res, + .num_resources = ARRAY_SIZE(alchemy_ac97c_res), +}; + +static struct platform_device alchemy_ac97c_dma_dev = { + .name = "alchemy-pcm-dma", + .id = 0, +}; + +static struct platform_device db1x00_codec_dev = { + .name = "ac97-codec", + .id = -1, +}; + +static struct platform_device db1x00_audio_dev = { + .name = "db1000-audio", +}; + +/******************************************************************************/ + +static irqreturn_t db1100_mmc_cd(int irq, void *ptr) +{ + void (*mmc_cd)(struct mmc_host *, unsigned long); + /* link against CONFIG_MMC=m */ + mmc_cd = symbol_get(mmc_detect_change); + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + + return IRQ_HANDLED; +} + +static int db1100_mmc_cd_setup(void *mmc_host, int en) +{ + int ret = 0; + + if (en) { + irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0, + "sd0_cd", mmc_host); + } else + free_irq(AU1100_GPIO19_INT, mmc_host); + return ret; +} + +static int db1100_mmc1_cd_setup(void *mmc_host, int en) +{ + int ret = 0; + + if (en) { + irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0, + "sd1_cd", mmc_host); + } else + free_irq(AU1100_GPIO20_INT, mmc_host); + return ret; +} + +static int db1100_mmc_card_readonly(void *mmc_host) +{ + /* testing suggests that this bit is inverted */ + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1; +} + +static int db1100_mmc_card_inserted(void *mmc_host) +{ + return !alchemy_gpio_get_value(19); +} + +static void db1100_mmc_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); +} + +static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) +{ + if (b != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1100_mmc_led = { + .brightness_set = db1100_mmcled_set, +}; + +static int db1100_mmc1_card_readonly(void *mmc_host) +{ + return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0; +} + +static int db1100_mmc1_card_inserted(void *mmc_host) +{ + return !alchemy_gpio_get_value(20); +} + +static void db1100_mmc1_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); +} + +static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) +{ + if (b != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev db1100_mmc1_led = { + .brightness_set = db1100_mmc1led_set, +}; + +static struct au1xmmc_platform_data db1100_mmc_platdata[2] = { + [0] = { + .cd_setup = db1100_mmc_cd_setup, + .set_power = db1100_mmc_set_power, + .card_inserted = db1100_mmc_card_inserted, + .card_readonly = db1100_mmc_card_readonly, + .led = &db1100_mmc_led, + }, + [1] = { + .cd_setup = db1100_mmc1_cd_setup, + .set_power = db1100_mmc1_set_power, + .card_inserted = db1100_mmc1_card_inserted, + .card_readonly = db1100_mmc1_card_readonly, + .led = &db1100_mmc1_led, + }, +}; + +static struct resource au1100_mmc0_resources[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_SD_INT, + .end = AU1100_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DMA_ID_SD0_TX, + .end = DMA_ID_SD0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMA_ID_SD0_RX, + .end = DMA_ID_SD0_RX, + .flags = IORESOURCE_DMA, + } +}; + +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1100_mmc0_dev = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1100_mmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au1100_mmc0_resources), + .resource = au1100_mmc0_resources, +}; + +static struct resource au1100_mmc1_res[] = { + [0] = { + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_SD_INT, + .end = AU1100_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DMA_ID_SD1_TX, + .end = DMA_ID_SD1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMA_ID_SD1_RX, + .end = DMA_ID_SD1_RX, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device db1100_mmc1_dev = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1100_mmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1100_mmc1_res), + .resource = au1100_mmc1_res, +}; + +/******************************************************************************/ + +static void db1000_irda_set_phy_mode(int mode) +{ + unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL; + + switch (mode) { + case AU1000_IRDA_PHY_MODE_OFF: + bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF); + break; + case AU1000_IRDA_PHY_MODE_SIR: + bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL); + break; + case AU1000_IRDA_PHY_MODE_FIR: + bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL | + BCSR_RESETS_FIR_SEL); + break; + } +} + +static struct au1k_irda_platform_data db1000_irda_platdata = { + .set_phy_mode = db1000_irda_set_phy_mode, +}; + +static struct resource au1000_irda_res[] = { + [0] = { + .start = AU1000_IRDA_PHYS_ADDR, + .end = AU1000_IRDA_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1000_IRDA_TX_INT, + .end = AU1000_IRDA_TX_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1000_IRDA_RX_INT, + .end = AU1000_IRDA_RX_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device db1000_irda_dev = { + .name = "au1000-irda", + .id = -1, + .dev = { + .platform_data = &db1000_irda_platdata, + }, + .resource = au1000_irda_res, + .num_resources = ARRAY_SIZE(au1000_irda_res), +}; + +/******************************************************************************/ + +static struct ads7846_platform_data db1100_touch_pd = { + .model = 7846, + .vref_mv = 3300, + .gpio_pendown = 21, +}; + +static struct spi_gpio_platform_data db1100_spictl_pd = { + .sck = 209, + .mosi = 208, + .miso = 207, + .num_chipselect = 1, +}; + +static struct spi_board_info db1100_spi_info[] __initdata = { + [0] = { + .modalias = "ads7846", + .max_speed_hz = 3250000, + .bus_num = 0, + .chip_select = 0, + .mode = 0, + .irq = AU1100_GPIO21_INT, + .platform_data = &db1100_touch_pd, + .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */ + }, +}; + +static struct platform_device db1100_spi_dev = { + .name = "spi_gpio", + .id = 0, + .dev = { + .platform_data = &db1100_spictl_pd, + }, +}; + + +static struct platform_device *db1x00_devs[] = { + &db1x00_codec_dev, + &alchemy_ac97c_dma_dev, + &alchemy_ac97c_dev, + &db1x00_audio_dev, +}; + +static struct platform_device *db1000_devs[] = { + &db1000_irda_dev, +}; + +static struct platform_device *db1100_devs[] = { + &au1100_lcd_device, + &db1100_mmc0_dev, + &db1100_mmc1_dev, + &db1000_irda_dev, + &db1100_spi_dev, +}; + +static int __init db1000_dev_init(void) +{ + int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + int c0, c1, d0, d1, s0, s1; + unsigned long pfc; + + if (board == BCSR_WHOAMI_DB1500) { + c0 = AU1500_GPIO2_INT; + c1 = AU1500_GPIO5_INT; + d0 = AU1500_GPIO0_INT; + d1 = AU1500_GPIO3_INT; + s0 = AU1500_GPIO1_INT; + s1 = AU1500_GPIO4_INT; + } else if (board == BCSR_WHOAMI_DB1100) { + c0 = AU1100_GPIO2_INT; + c1 = AU1100_GPIO5_INT; + d0 = AU1100_GPIO0_INT; + d1 = AU1100_GPIO3_INT; + s0 = AU1100_GPIO1_INT; + s1 = AU1100_GPIO4_INT; + + gpio_direction_input(19); /* sd0 cd# */ + gpio_direction_input(20); /* sd1 cd# */ + gpio_direction_input(21); /* touch pendown# */ + gpio_direction_input(207); /* SPI MISO */ + gpio_direction_output(208, 0); /* SPI MOSI */ + gpio_direction_output(209, 1); /* SPI SCK */ + gpio_direction_output(210, 1); /* SPI CS# */ + + /* spi_gpio on SSI0 pins */ + pfc = __raw_readl((void __iomem *)SYS_PINFUNC); + pfc |= (1 << 0); /* SSI0 pins as GPIOs */ + __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); + wmb(); + + spi_register_board_info(db1100_spi_info, + ARRAY_SIZE(db1100_spi_info)); + + platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); + } else if (board == BCSR_WHOAMI_DB1000) { + c0 = AU1000_GPIO2_INT; + c1 = AU1000_GPIO5_INT; + d0 = AU1000_GPIO0_INT; + d1 = AU1000_GPIO3_INT; + s0 = AU1000_GPIO1_INT; + s1 = AU1000_GPIO4_INT; + platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs)); + } else + return 0; /* unknown board, no further dev setup to do */ + + irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + c0, d0, /*s0*/0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + c1, d1, /*s1*/0, 0, 1); + + platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); + db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); + return 0; +} +device_initcall(db1000_dev_init); diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200.c index 78459c17c62..a83302b96c0 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -1,7 +1,7 @@ /* - * DBAu1200 board platform device registration + * DBAu1200/PBAu1200 board platform device registration * - * Copyright (C) 2008-2009 Manuel Lauss + * Copyright (C) 2008-2011 Manuel Lauss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +22,7 @@ #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/init.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/leds.h> #include <linux/mmc/host.h> @@ -33,18 +34,116 @@ #include <linux/spi/spi.h> #include <linux/spi/flash.h> #include <linux/smc91x.h> - +#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1100_mmc.h> #include <asm/mach-au1x00/au1xxx_dbdma.h> +#include <asm/mach-au1x00/au1200fb.h> #include <asm/mach-au1x00/au1550_spi.h> #include <asm/mach-db1x00/bcsr.h> #include <asm/mach-db1x00/db1200.h> -#include "../platform.h" +#include "platform.h" + +static const char *board_type_str(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_PB1200_DDR1: + case BCSR_WHOAMI_PB1200_DDR2: + return "PB1200"; + case BCSR_WHOAMI_DB1200: + return "DB1200"; + default: + return "(unknown)"; + } +} + +const char *get_system_type(void) +{ + return board_type_str(); +} + +static int __init detect_board(void) +{ + int bid; + + /* try the DB1200 first */ + bcsr_init(DB1200_BCSR_PHYS_ADDR, + DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); + if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + unsigned short t = bcsr_read(BCSR_HEXLEDS); + bcsr_write(BCSR_HEXLEDS, ~t); + if (bcsr_read(BCSR_HEXLEDS) != t) { + bcsr_write(BCSR_HEXLEDS, t); + return 0; + } + } + + /* okay, try the PB1200 then */ + bcsr_init(PB1200_BCSR_PHYS_ADDR, + PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); + bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + if ((bid == BCSR_WHOAMI_PB1200_DDR1) || + (bid == BCSR_WHOAMI_PB1200_DDR2)) { + unsigned short t = bcsr_read(BCSR_HEXLEDS); + bcsr_write(BCSR_HEXLEDS, ~t); + if (bcsr_read(BCSR_HEXLEDS) != t) { + bcsr_write(BCSR_HEXLEDS, t); + return 0; + } + } + + return 1; /* it's neither */ +} + +void __init board_setup(void) +{ + unsigned long freq0, clksrc, div, pfc; + unsigned short whoami; + + if (detect_board()) { + printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n"); + return; + } + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", board_type_str(), + (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); + + /* SMBus/SPI on PSC0, Audio on PSC1 */ + pfc = __raw_readl((void __iomem *)SYS_PINFUNC); + pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); + pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); + pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ + __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); + wmb(); + + /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from + * CPU clock; all other clock generators off/unused. + */ + div = (get_au1x00_speed() + 25000000) / 50000000; + if (div & 1) + div++; + div = ((div >> 1) - 1) & 0xff; + + freq0 = div << SYS_FC_FRDIV0_BIT; + __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); + wmb(); + freq0 |= SYS_FC_FE0; /* enable F0 */ + __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); + wmb(); + + /* psc0_intclk comes 1:1 from F0 */ + clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; + __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); + wmb(); +} + +/******************************************************************************/ static struct mtd_partition db1200_spiflash_parts[] = { { - .name = "DB1200 SPI flash", + .name = "spi_flash", .offset = 0, .size = MTDPART_SIZ_FULL, }, @@ -78,18 +177,9 @@ static struct spi_board_info db1200_spi_devs[] __initdata = { }; static struct i2c_board_info db1200_i2c_devs[] __initdata = { - { - /* AT24C04-10 I2C eeprom */ - I2C_BOARD_INFO("24c04", 0x52), - }, - { - /* Philips NE1619 temp/voltage sensor (adm1025 drv) */ - I2C_BOARD_INFO("ne1619", 0x2d), - }, - { - /* I2S audio codec WM8731 */ - I2C_BOARD_INFO("wm8731", 0x1b), - }, + { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ + { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ + { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ }; /**********************************************************************/ @@ -206,7 +296,7 @@ static struct platform_device db1200_eth_dev = { static struct resource db1200_ide_res[] = { [0] = { .start = DB1200_IDE_PHYS_ADDR, - .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, + .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -221,13 +311,13 @@ static struct resource db1200_ide_res[] = { }, }; -static u64 ide_dmamask = DMA_BIT_MASK(32); +static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); static struct platform_device db1200_ide_dev = { .name = "au1200-ide", .id = 0, .dev = { - .dma_mask = &ide_dmamask, + .dma_mask = &au1200_ide_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(db1200_ide_res), @@ -236,13 +326,6 @@ static struct platform_device db1200_ide_dev = { /**********************************************************************/ -static struct platform_device db1200_rtc_dev = { - .name = "rtc-au1xxx", - .id = -1, -}; - -/**********************************************************************/ - /* SD carddetects: they're supposed to be edge-triggered, but ack * doesn't seem to work (CPLD Rev 2). Instead, the screaming one * is disabled and its counterpart enabled. The 500ms timeout is @@ -333,12 +416,109 @@ static struct led_classdev db1200_mmc_led = { .brightness_set = db1200_mmcled_set, }; -static struct au1xmmc_platform_data db1200mmc_platdata = { - .cd_setup = db1200_mmc_cd_setup, - .set_power = db1200_mmc_set_power, - .card_inserted = db1200_mmc_card_inserted, - .card_readonly = db1200_mmc_card_readonly, - .led = &db1200_mmc_led, +/* -- */ + +static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + if (irq == PB1200_SD1_INSERT_INT) { + disable_irq_nosync(PB1200_SD1_INSERT_INT); + enable_irq(PB1200_SD1_EJECT_INT); + } else { + disable_irq_nosync(PB1200_SD1_EJECT_INT); + enable_irq(PB1200_SD1_INSERT_INT); + } + + /* link against CONFIG_MMC=m */ + mmc_cd = symbol_get(mmc_detect_change); + if (mmc_cd) { + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + } + + return IRQ_HANDLED; +} + +static int pb1200_mmc1_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0, + "sd1_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0, + "sd1_eject", mmc_host); + if (ret) { + free_irq(PB1200_SD1_INSERT_INT, mmc_host); + goto out; + } + + if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) + enable_irq(PB1200_SD1_EJECT_INT); + else + enable_irq(PB1200_SD1_INSERT_INT); + + } else { + free_irq(PB1200_SD1_INSERT_INT, mmc_host); + free_irq(PB1200_SD1_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static void pb1200_mmc1led_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev pb1200_mmc1_led = { + .brightness_set = pb1200_mmc1led_set, +}; + +static void pb1200_mmc1_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); +} + +static int pb1200_mmc1_card_readonly(void *mmc_host) +{ + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; +} + +static int pb1200_mmc1_card_inserted(void *mmc_host) +{ + return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; +} + + +static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { + [0] = { + .cd_setup = db1200_mmc_cd_setup, + .set_power = db1200_mmc_set_power, + .card_inserted = db1200_mmc_card_inserted, + .card_readonly = db1200_mmc_card_readonly, + .led = &db1200_mmc_led, + }, + [1] = { + .cd_setup = pb1200_mmc1_cd_setup, + .set_power = pb1200_mmc1_set_power, + .card_inserted = pb1200_mmc1_card_inserted, + .card_readonly = pb1200_mmc1_card_readonly, + .led = &pb1200_mmc1_led, + }, }; static struct resource au1200_mmc0_resources[] = { @@ -372,14 +552,76 @@ static struct platform_device db1200_mmc0_dev = { .dev = { .dma_mask = &au1xxx_mmc_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &db1200mmc_platdata, + .platform_data = &db1200_mmc_platdata[0], }, .num_resources = ARRAY_SIZE(au1200_mmc0_resources), .resource = au1200_mmc0_resources, }; +static struct resource au1200_mmc1_res[] = { + [0] = { + .start = AU1100_SD1_PHYS_ADDR, + .end = AU1100_SD1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1200_DSCR_CMD0_SDMS_TX1, + .end = AU1200_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1200_DSCR_CMD0_SDMS_RX1, + .end = AU1200_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device pb1200_mmc1_dev = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200_mmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_res), + .resource = au1200_mmc1_res, +}; + /**********************************************************************/ +static int db1200fb_panel_index(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +static int db1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +static int db1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} + +static struct au1200fb_platdata db1200fb_pd = { + .panel_index = db1200fb_panel_index, + .panel_init = db1200fb_panel_init, + .panel_shutdown = db1200fb_panel_shutdown, +}; + static struct resource au1200_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -401,6 +643,7 @@ static struct platform_device au1200_lcd_dev = { .dev = { .dma_mask = &au1200_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200fb_pd, }, .num_resources = ARRAY_SIZE(au1200_lcd_res), .resource = au1200_lcd_res, @@ -519,7 +762,6 @@ static struct platform_device *db1200_devs[] __initdata = { &db1200_mmc0_dev, &au1200_lcd_dev, &db1200_eth_dev, - &db1200_rtc_dev, &db1200_nand_dev, &db1200_audiodma_dev, &db1200_audio_dev, @@ -527,11 +769,62 @@ static struct platform_device *db1200_devs[] __initdata = { &db1200_sound_dev, }; +static struct platform_device *pb1200_devs[] __initdata = { + &pb1200_mmc1_dev, +}; + +/* Some peripheral base addresses differ on the PB1200 */ +static int __init pb1200_res_fixup(void) +{ + /* CPLD Revs earlier than 4 cause problems */ + if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); + printk(KERN_ERR "the board updated to latest revisions.\n"); + printk(KERN_ERR "This software will not work reliably\n"); + printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); + printk(KERN_ERR "WARNING!!!\n"); + printk(KERN_ERR "WARNING!!!\n"); + return 1; + } + + db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; + db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; + db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; + db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; + db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; + db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; + return 0; +} + static int __init db1200_dev_init(void) { unsigned long pfc; unsigned short sw; - int swapped; + int swapped, bid; + + bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + if ((bid == BCSR_WHOAMI_PB1200_DDR1) || + (bid == BCSR_WHOAMI_PB1200_DDR2)) { + if (pb1200_res_fixup()) + return -ENODEV; + } + + /* GPIO7 is low-level triggered CPLD cascade */ + irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); + bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); + + /* insert/eject pairs: one of both is always screaming. To avoid + * issues they must not be automatically enabled when initially + * requested. + */ + irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); i2c_register_board_info(0, db1200_i2c_devs, ARRAY_SIZE(db1200_i2c_devs)); @@ -540,6 +833,7 @@ static int __init db1200_dev_init(void) /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) + * or S12 on the PB1200. */ /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however @@ -554,7 +848,7 @@ static int __init db1200_dev_init(void) gpio_request(215, "otg-vbus"); gpio_direction_output(215, 1); - printk(KERN_INFO "DB1200 device configuration:\n"); + printk(KERN_INFO "%s device configuration:\n", board_type_str()); sw = bcsr_read(BCSR_SWITCHES); if (sw & BCSR_SWITCHES_DIP_8) { @@ -595,7 +889,7 @@ static int __init db1200_dev_init(void) /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ __raw_writel(PSC_SEL_CLK_SERCLK, - (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); wmb(); db1x_register_pcmcia_socket( @@ -621,28 +915,13 @@ static int __init db1200_dev_init(void) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; db1x_register_norflash(64 << 20, 2, swapped); - return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); -} -device_initcall(db1200_dev_init); - -/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} + platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - return 0; -} + /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ + if ((bid == BCSR_WHOAMI_PB1200_DDR1) || + (bid == BCSR_WHOAMI_PB1200_DDR2)) + platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); return 0; } +device_initcall(db1200_dev_init); diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile deleted file mode 100644 index 17840a5e273..00000000000 --- a/arch/mips/alchemy/devboards/db1200/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c deleted file mode 100644 index 4a8980027ec..00000000000 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Alchemy/AMD/RMI DB1200 board setup. - * - * Licensed under the terms outlined in the file COPYING in the root of - * this source archive. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-db1x00/bcsr.h> -#include <asm/mach-db1x00/db1200.h> - -const char *get_system_type(void) -{ - return "Alchemy Db1200"; -} - -void __init board_setup(void) -{ - unsigned long freq0, clksrc, div, pfc; - unsigned short whoami; - - bcsr_init(DB1200_BCSR_PHYS_ADDR, - DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); - - whoami = bcsr_read(BCSR_WHOAMI); - printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" - " Board-ID %d Daughtercard ID %d\n", - (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); - - /* SMBus/SPI on PSC0, Audio on PSC1 */ - pfc = __raw_readl((void __iomem *)SYS_PINFUNC); - pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); - pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); - pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ - __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); - wmb(); - - /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from - * CPU clock; all other clock generators off/unused. - */ - div = (get_au1x00_speed() + 25000000) / 50000000; - if (div & 1) - div++; - div = ((div >> 1) - 1) & 0xff; - - freq0 = div << SYS_FC_FRDIV0_BIT; - __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); - wmb(); - freq0 |= SYS_FC_FE0; /* enable F0 */ - __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); - wmb(); - - /* psc0_intclk comes 1:1 from F0 */ - clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; - __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); - wmb(); -} - -static int __init db1200_arch_init(void) -{ - /* GPIO7 is low-level triggered CPLD cascade */ - irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); - bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); - - /* insert/eject pairs: one of both is always screaming. To avoid - * issues they must not be automatically enabled when initially - * requested. - */ - irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); - irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); - return 0; -} -arch_initcall(db1200_arch_init); diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c new file mode 100644 index 00000000000..0893f2af0d0 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300.c @@ -0,0 +1,785 @@ +/* + * DBAu1300 init and platform device setup. + * + * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com> + */ + +#include <linux/dma-mapping.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/init.h> +#include <linux/input.h> /* KEY_* codes */ +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/leds.h> +#include <linux/ata_platform.h> +#include <linux/mmc/host.h> +#include <linux/module.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/smsc911x.h> + +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1100_mmc.h> +#include <asm/mach-au1x00/au1200fb.h> +#include <asm/mach-au1x00/au1xxx_dbdma.h> +#include <asm/mach-au1x00/au1xxx_psc.h> +#include <asm/mach-db1x00/db1300.h> +#include <asm/mach-db1x00/bcsr.h> +#include <asm/mach-au1x00/prom.h> + +#include "platform.h" + +static struct i2c_board_info db1300_i2c_devs[] __initdata = { + { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ + { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ +}; + +/* multifunction pins to assign to GPIO controller */ +static int db1300_gpio_pins[] __initdata = { + AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, + AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, + AU1300_PIN_EXTCLK1, + -1, /* terminator */ +}; + +/* multifunction pins to assign to device functions */ +static int db1300_dev_pins[] __initdata = { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0, + /* external clock sources for PSC0 */ + AU1300_PIN_EXTCLK0, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 30-31 */ + AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, + -1, /* terminator */ +}; + +static void __init db1300_gpio_config(void) +{ + int *i; + + i = &db1300_dev_pins[0]; + while (*i != -1) + au1300_pinfunc_to_dev(*i++); + + i = &db1300_gpio_pins[0]; + while (*i != -1) + au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ + + au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); +} + +char *get_system_type(void) +{ + return "DB1300"; +} + +/**********************************************************************/ + +static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1300_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1300_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1300_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1300_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1300_nand_parts), + .partitions = db1300_nand_parts, + .chip_delay = 20, + .part_probe_types = db1300_part_probes, + }, + .ctrl = { + .dev_ready = au1300_nand_device_ready, + .cmd_ctrl = au1300_nand_cmd_ctrl, + }, +}; + +static struct resource db1300_nand_res[] = { + [0] = { + .start = DB1300_NAND_PHYS_ADDR, + .end = DB1300_NAND_PHYS_ADDR + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1300_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1300_nand_res), + .resource = db1300_nand_res, + .id = -1, + .dev = { + .platform_data = &db1300_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct resource db1300_eth_res[] = { + [0] = { + .start = DB1300_ETH_PHYS_ADDR, + .end = DB1300_ETH_PHYS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_ETH_INT, + .end = DB1300_ETH_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config db1300_eth_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device db1300_eth_dev = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(db1300_eth_res), + .resource = db1300_eth_res, + .dev = { + .platform_data = &db1300_eth_config, + }, +}; + +/**********************************************************************/ + +static struct resource au1300_psc1_res[] = { + [0] = { + .start = AU1300_PSC1_PHYS_ADDR, + .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC1_INT, + .end = AU1300_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC1_TX, + .end = AU1300_DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC1_RX, + .end = AU1300_DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 1, /* PSC ID. match with AC97 codec ID! */ + .num_resources = ARRAY_SIZE(au1300_psc1_res), + .resource = au1300_psc1_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc2_res[] = { + [0] = { + .start = AU1300_PSC2_PHYS_ADDR, + .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC2_INT, + .end = AU1300_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC2_TX, + .end = AU1300_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC2_RX, + .end = AU1300_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 2, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1300_psc2_res), + .resource = au1300_psc2_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc3_res[] = { + [0] = { + .start = AU1300_PSC3_PHYS_ADDR, + .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC3_INT, + .end = AU1300_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC3_TX, + .end = AU1300_DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC3_RX, + .end = AU1300_DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1300_psc3_res), + .resource = au1300_psc3_res, +}; + +/**********************************************************************/ + +/* proper key assignments when facing the LCD panel. For key assignments + * according to the schematics swap up with down and left with right. + * I chose to use it to emulate the arrow keys of a keyboard. + */ +static struct gpio_keys_button db1300_5waysw_arrowkeys[] = { + { + .code = KEY_DOWN, + .gpio = AU1300_PIN_LCDPWM0, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-down", + }, + { + .code = KEY_UP, + .gpio = AU1300_PIN_PSC2SYNC1, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-up", + }, + { + .code = KEY_RIGHT, + .gpio = AU1300_PIN_WAKE3, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-right", + }, + { + .code = KEY_LEFT, + .gpio = AU1300_PIN_WAKE2, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-left", + }, + { + .code = KEY_ENTER, + .gpio = AU1300_PIN_WAKE1, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-push", + }, +}; + +static struct gpio_keys_platform_data db1300_5waysw_data = { + .buttons = db1300_5waysw_arrowkeys, + .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys), + .rep = 1, + .name = "db1300-5wayswitch", +}; + +static struct platform_device db1300_5waysw_dev = { + .name = "gpio-keys", + .dev = { + .platform_data = &db1300_5waysw_data, + }, +}; + +/**********************************************************************/ + +static struct pata_platform_info db1300_ide_info = { + .ioport_shift = DB1300_IDE_REG_SHIFT, +}; + +#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) +static struct resource db1300_ide_res[] = { + [0] = { + .start = DB1300_IDE_PHYS_ADDR, + .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, + .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = DB1300_IDE_INT, + .end = DB1300_IDE_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device db1300_ide_dev = { + .dev = { + .platform_data = &db1300_ide_info, + }, + .name = "pata_platform", + .resource = db1300_ide_res, + .num_resources = ARRAY_SIZE(db1300_ide_res), +}; + +/**********************************************************************/ + +static irqreturn_t db1300_mmc_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + /* disable the one currently screaming. No other way to shut it up */ + if (irq == DB1300_SD1_INSERT_INT) { + disable_irq_nosync(DB1300_SD1_INSERT_INT); + enable_irq(DB1300_SD1_EJECT_INT); + } else { + disable_irq_nosync(DB1300_SD1_EJECT_INT); + enable_irq(DB1300_SD1_INSERT_INT); + } + + /* link against CONFIG_MMC=m. We can only be called once MMC core has + * initialized the controller, so symbol_get() should always succeed. + */ + mmc_cd = symbol_get(mmc_detect_change); + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + + return IRQ_HANDLED; +} + +static int db1300_mmc_card_readonly(void *mmc_host) +{ + /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */ + return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP; +} + +static int db1300_mmc_card_inserted(void *mmc_host) +{ + return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */ +} + +static int db1300_mmc_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0, + "sd_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0, + "sd_eject", mmc_host); + if (ret) { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + goto out; + } + + if (db1300_mmc_card_inserted(mmc_host)) + enable_irq(DB1300_SD1_EJECT_INT); + else + enable_irq(DB1300_SD1_INSERT_INT); + + } else { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + free_irq(DB1300_SD1_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1300_mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + +struct au1xmmc_platform_data db1300_sd1_platdata = { + .cd_setup = db1300_mmc_cd_setup, + .card_inserted = db1300_mmc_card_inserted, + .card_readonly = db1300_mmc_card_readonly, + .led = &db1300_mmc_led, +}; + +static struct resource au1300_sd1_res[] = { + [0] = { + .start = AU1300_SD1_PHYS_ADDR, + .end = AU1300_SD1_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD1_INT, + .end = AU1300_SD1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_SDMS_TX1, + .end = AU1300_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_SDMS_RX1, + .end = AU1300_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd1_dev = { + .dev = { + .platform_data = &db1300_sd1_platdata, + }, + .name = "au1xxx-mmc", + .id = 1, + .resource = au1300_sd1_res, + .num_resources = ARRAY_SIZE(au1300_sd1_res), +}; + +/**********************************************************************/ + +static int db1300_movinand_inserted(void *mmc_host) +{ + return 0; /* disable for now, it doesn't work yet */ +} + +static int db1300_movinand_readonly(void *mmc_host) +{ + return 0; +} + +static void db1300_movinand_led_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev db1300_movinand_led = { + .brightness_set = db1300_movinand_led_set, +}; + +struct au1xmmc_platform_data db1300_sd0_platdata = { + .card_inserted = db1300_movinand_inserted, + .card_readonly = db1300_movinand_readonly, + .led = &db1300_movinand_led, + .mask_host_caps = MMC_CAP_NEEDS_POLL, +}; + +static struct resource au1300_sd0_res[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD0_INT, + .end = AU1300_SD0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_SDMS_TX0, + .end = AU1300_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_SDMS_RX0, + .end = AU1300_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd0_dev = { + .dev = { + .platform_data = &db1300_sd0_platdata, + }, + .name = "au1xxx-mmc", + .id = 0, + .resource = au1300_sd0_res, + .num_resources = ARRAY_SIZE(au1300_sd0_res), +}; + +/**********************************************************************/ + +static struct platform_device db1300_wm9715_dev = { + .name = "wm9712-codec", + .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */ +}; + +static struct platform_device db1300_ac97dma_dev = { + .name = "au1xpsc-pcm", + .id = 1, /* PSC ID */ +}; + +static struct platform_device db1300_i2sdma_dev = { + .name = "au1xpsc-pcm", + .id = 2, /* PSC ID */ +}; + +static struct platform_device db1300_sndac97_dev = { + .name = "db1300-ac97", +}; + +static struct platform_device db1300_sndi2s_dev = { + .name = "db1300-i2s", +}; + +/**********************************************************************/ + +static int db1300fb_panel_index(void) +{ + return 9; /* DB1300_800x480 */ +} + +static int db1300fb_panel_init(void) +{ + /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, + BCSR_BOARD_LCDBL); + return 0; +} + +static int db1300fb_panel_shutdown(void) +{ + /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, + BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); + return 0; +} + +static struct au1200fb_platdata db1300fb_pd = { + .panel_index = db1300fb_panel_index, + .panel_init = db1300fb_panel_init, + .panel_shutdown = db1300fb_panel_shutdown, +}; + +static struct resource au1300_lcd_res[] = { + [0] = { + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_LCD_INT, + .end = AU1300_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1300_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1300_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1300fb_pd, + }, + .num_resources = ARRAY_SIZE(au1300_lcd_res), + .resource = au1300_lcd_res, +}; + +/**********************************************************************/ + +static struct platform_device *db1300_dev[] __initdata = { + &db1300_eth_dev, + &db1300_i2c_dev, + &db1300_5waysw_dev, + &db1300_nand_dev, + &db1300_ide_dev, + &db1300_sd0_dev, + &db1300_sd1_dev, + &db1300_lcd_dev, + &db1300_ac97_dev, + &db1300_i2s_dev, + &db1300_wm9715_dev, + &db1300_ac97dma_dev, + &db1300_i2sdma_dev, + &db1300_sndac97_dev, + &db1300_sndi2s_dev, +}; + +static int __init db1300_device_init(void) +{ + int swapped, cpldirq; + + /* setup CPLD IRQ muxer */ + cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); + irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); + bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); + + /* insert/eject IRQs: one always triggers so don't enable them + * when doing request_irq() on them. DB1200 has this bug too. + */ + irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); + + /* + * setup board + */ + prom_get_ethernet_addr(&db1300_eth_config.mac[0]); + + i2c_register_board_info(0, db1300_i2c_devs, + ARRAY_SIZE(db1300_i2c_devs)); + + /* Audio PSC clock is supplied by codecs (PSC1, 2) */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + /* I2C uses internal 48MHz EXTCLK1 */ + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + /* enable power to USB ports */ + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); + + /* although it is socket #0, it uses the CPLD bits which previous boards + * have used for socket #1. + */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, + DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; + db1x_register_norflash(64 << 20, 2, swapped); + + return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); +} +device_initcall(db1300_device_init); + + +void __init board_setup(void) +{ + unsigned short whoami; + + db1300_gpio_config(); + bcsr_init(DB1300_BCSR_PHYS_ADDR, + DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" + "BoardID %d CPLD Rev %d DaughtercardID %d\n", + BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), + BCSR_WHOAMI_DCID(whoami)); + + /* enable UARTs, YAMON only enables #2 */ + alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); + alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); + alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); +} diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c new file mode 100644 index 00000000000..6815d0783cd --- /dev/null +++ b/arch/mips/alchemy/devboards/db1550.c @@ -0,0 +1,498 @@ +/* + * Alchemy Db1550 board support + * + * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com> + */ + +#include <linux/dma-mapping.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/au1xxx_eth.h> +#include <asm/mach-au1x00/au1xxx_dbdma.h> +#include <asm/mach-au1x00/au1xxx_psc.h> +#include <asm/mach-au1x00/au1550_spi.h> +#include <asm/mach-db1x00/bcsr.h> +#include <prom.h> +#include "platform.h" + + +const char *get_system_type(void) +{ + return "DB1550"; +} + +static void __init db1550_hw_setup(void) +{ + void __iomem *base; + + alchemy_gpio_direction_output(203, 0); /* red led on */ + + /* complete SPI setup: link psc0_intclk to a 48MHz source, + * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) + */ + base = (void __iomem *)SYS_CLKSRC; + __raw_writel(__raw_readl(base) | 0x000001e0, base); + base = (void __iomem *)SYS_PINFUNC; + __raw_writel(__raw_readl(base) | 1, base); + wmb(); + + /* reset the AC97 codec now, the reset time in the psc-ac97 driver + * is apparently too short although it's ridiculous as it is. + */ + base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); + __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, + base + PSC_SEL_OFFSET); + __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); + wmb(); + __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); + wmb(); + + alchemy_gpio_direction_output(202, 0); /* green led on */ +} + +void __init board_setup(void) +{ + unsigned short whoami; + + bcsr_init(DB1550_BCSR_PHYS_ADDR, + DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", + (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); + + db1550_hw_setup(); +} + +/*****************************************************************************/ + +static struct mtd_partition db1550_spiflash_parts[] = { + { + .name = "spi_flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data db1550_spiflash_data = { + .name = "s25fl010", + .parts = db1550_spiflash_parts, + .nr_parts = ARRAY_SIZE(db1550_spiflash_parts), + .type = "m25p10", +}; + +static struct spi_board_info db1550_spi_devs[] __initdata = { + { + /* TI TMP121AIDBVR temp sensor */ + .modalias = "tmp121", + .max_speed_hz = 2400000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + }, + { + /* Spansion S25FL001D0FMA SPI flash */ + .modalias = "m25p80", + .max_speed_hz = 2400000, + .bus_num = 0, + .chip_select = 1, + .mode = SPI_MODE_0, + .platform_data = &db1550_spiflash_data, + }, +}; + +static struct i2c_board_info db1550_i2c_devs[] __initdata = { + { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */ + { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */ + { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */ +}; + +/**********************************************************************/ + +static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1550_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1550_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1550_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1550_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1550_nand_parts), + .partitions = db1550_nand_parts, + .chip_delay = 20, + .part_probe_types = db1550_part_probes, + }, + .ctrl = { + .dev_ready = au1550_nand_device_ready, + .cmd_ctrl = au1550_nand_cmd_ctrl, + }, +}; + +static struct resource db1550_nand_res[] = { + [0] = { + .start = 0x20000000, + .end = 0x200000ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1550_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1550_nand_res), + .resource = db1550_nand_res, + .id = -1, + .dev = { + .platform_data = &db1550_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct resource au1550_psc0_res[] = { + [0] = { + .start = AU1550_PSC0_PHYS_ADDR, + .end = AU1550_PSC0_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC0_INT, + .end = AU1550_PSC0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC0_TX, + .end = AU1550_DSCR_CMD0_PSC0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC0_RX, + .end = AU1550_DSCR_CMD0_PSC0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) +{ + if (cs) + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL); + else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0); +} + +static struct au1550_spi_info db1550_spi_platdata = { + .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */ + .num_chipselect = 2, + .activate_cs = db1550_spi_cs_en, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1550_spi_dev = { + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1550_spi_platdata, + }, + .name = "au1550-spi", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1550_psc0_res), + .resource = au1550_psc0_res, +}; + +/**********************************************************************/ + +static struct resource au1550_psc1_res[] = { + [0] = { + .start = AU1550_PSC1_PHYS_ADDR, + .end = AU1550_PSC1_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC1_INT, + .end = AU1550_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC1_TX, + .end = AU1550_DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC1_RX, + .end = AU1550_DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1550_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 1, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1550_psc1_res), + .resource = au1550_psc1_res, +}; + + +static struct resource au1550_psc2_res[] = { + [0] = { + .start = AU1550_PSC2_PHYS_ADDR, + .end = AU1550_PSC2_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC2_INT, + .end = AU1550_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC2_TX, + .end = AU1550_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC2_RX, + .end = AU1550_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1550_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1550_psc2_res), + .resource = au1550_psc2_res, +}; + +/**********************************************************************/ + +static struct resource au1550_psc3_res[] = { + [0] = { + .start = AU1550_PSC3_PHYS_ADDR, + .end = AU1550_PSC3_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1550_PSC3_INT, + .end = AU1550_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1550_DSCR_CMD0_PSC3_TX, + .end = AU1550_DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1550_DSCR_CMD0_PSC3_RX, + .end = AU1550_DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1550_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 3, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1550_psc3_res), + .resource = au1550_psc3_res, +}; + +/**********************************************************************/ + +static struct platform_device db1550_stac_dev = { + .name = "ac97-codec", + .id = 1, /* on PSC1 */ +}; + +static struct platform_device db1550_ac97dma_dev = { + .name = "au1xpsc-pcm", + .id = 1, /* on PSC3 */ +}; + +static struct platform_device db1550_i2sdma_dev = { + .name = "au1xpsc-pcm", + .id = 3, /* on PSC3 */ +}; + +static struct platform_device db1550_sndac97_dev = { + .name = "db1550-ac97", +}; + +static struct platform_device db1550_sndi2s_dev = { + .name = "db1550-i2s", +}; + +/**********************************************************************/ + +static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 11) || (slot > 13) || pin == 0) + return -1; + if (slot == 11) + return (pin == 1) ? AU1550_PCI_INTC : 0xff; + if (slot == 12) { + switch (pin) { + case 1: return AU1550_PCI_INTB; + case 2: return AU1550_PCI_INTC; + case 3: return AU1550_PCI_INTD; + case 4: return AU1550_PCI_INTA; + } + } + if (slot == 13) { + switch (pin) { + case 1: return AU1550_PCI_INTA; + case 2: return AU1550_PCI_INTB; + case 3: return AU1550_PCI_INTC; + case 4: return AU1550_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1550_pci_pd = { + .board_map_irq = db1550_map_pci_irq, +}; + +static struct platform_device db1550_pci_host_dev = { + .dev.platform_data = &db1550_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +/**********************************************************************/ + +static struct platform_device *db1550_devs[] __initdata = { + &db1550_nand_dev, + &db1550_i2c_dev, + &db1550_ac97_dev, + &db1550_spi_dev, + &db1550_i2s_dev, + &db1550_stac_dev, + &db1550_ac97dma_dev, + &db1550_i2sdma_dev, + &db1550_sndac97_dev, + &db1550_sndi2s_dev, +}; + +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +static int __init db1550_pci_init(void) +{ + return platform_device_register(&db1550_pci_host_dev); +} +arch_initcall(db1550_pci_init); + +static int __init db1550_dev_init(void) +{ + int swapped; + + irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ + irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ + irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ + irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ + irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ + irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ + + i2c_register_board_info(0, db1550_i2c_devs, + ARRAY_SIZE(db1550_i2c_devs)); + spi_register_board_info(db1550_spi_devs, + ARRAY_SIZE(db1550_i2c_devs)); + + /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + /* SPI/I2C use internally supplied 50MHz source */ + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1550_GPIO3_INT, AU1550_GPIO0_INT, + /*AU1550_GPIO21_INT*/0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + AU1550_GPIO5_INT, AU1550_GPIO1_INT, + /*AU1550_GPIO22_INT*/0, 0, 1); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(128 << 20, 4, swapped); + + return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); +} +device_initcall(db1550_dev_init); diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile deleted file mode 100644 index 613c0c0c8be..00000000000 --- a/arch/mips/alchemy/devboards/db1x00/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for the Alchemy Semiconductor DBAu1xx0 boards. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c deleted file mode 100644 index 7cd36e631f6..00000000000 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Alchemy Db1x00 board setup. - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/pm.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1xxx_eth.h> -#include <asm/mach-db1x00/db1x00.h> -#include <asm/mach-db1x00/bcsr.h> -#include <asm/reboot.h> - -#include <prom.h> - -#ifdef CONFIG_MIPS_BOSPORUS -char irq_tab_alchemy[][5] __initdata = { - [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ - [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */ - [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ -}; - -/* - * Micrel/Kendin 5 port switch attached to MAC0, - * MAC0 is associated with PHY address 5 (== WAN port) - * MAC1 is not associated with any PHY, since it's connected directly - * to the switch. - * no interrupts are used - */ -static struct au1000_eth_platform_data eth0_pdata = { - .phy_static_config = 1, - .phy_addr = 5, -}; - -static void bosporus_power_off(void) -{ - while (1) - asm volatile (".set mips3 ; wait ; .set mips0"); -} - -const char *get_system_type(void) -{ - return "Alchemy Bosporus Gateway Reference"; -} -#endif - - -#ifdef CONFIG_MIPS_MIRAGE -static void mirage_power_off(void) -{ - alchemy_gpio_direction_output(210, 1); -} - -const char *get_system_type(void) -{ - return "Alchemy Mirage"; -} -#endif - - -#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) -static void mips_softreset(void) -{ - asm volatile ("jr\t%0" : : "r"(0xbfc00000)); -} - -#else - -const char *get_system_type(void) -{ - return "Alchemy Db1x00"; -} -#endif - - -void __init board_setup(void) -{ - unsigned long bcsr1, bcsr2; - - bcsr1 = DB1000_BCSR_PHYS_ADDR; - bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; - -#ifdef CONFIG_MIPS_DB1000 - printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1500 - printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1100 - printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); -#endif -#ifdef CONFIG_MIPS_BOSPORUS - au1xxx_override_eth_cfg(0, ð0_pdata); - - printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); -#endif -#ifdef CONFIG_MIPS_MIRAGE - printk(KERN_INFO "AMD Alchemy Mirage Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1550 - printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); - - bcsr1 = DB1550_BCSR_PHYS_ADDR; - bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS; -#endif - - /* initialize board register space */ - bcsr_init(bcsr1, bcsr2); - -#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) - { - u32 pin_func; - - /* Set IRFIRSEL instead of GPIO15 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; - au_writel(pin_func, SYS_PINFUNC); - /* Power off until the driver is in use */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, - BCSR_RESETS_IRDA_MODE_OFF); - } -#endif - bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ - - /* Enable GPIO[31:0] inputs */ - alchemy_gpio1_input_enable(); - -#ifdef CONFIG_MIPS_MIRAGE - { - u32 pin_func; - - /* GPIO[20] is output */ - alchemy_gpio_direction_output(20, 0); - - /* Set GPIO[210:208] instead of SSI_0 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; - - /* Set GPIO[215:211] for LEDs */ - pin_func |= 5 << 2; - - /* Set GPIO[214:213] for more LEDs */ - pin_func |= 5 << 12; - - /* Set GPIO[207:200] instead of PCMCIA/LCD */ - pin_func |= SYS_PF_LCD | SYS_PF_PC; - au_writel(pin_func, SYS_PINFUNC); - - /* - * Enable speaker amplifier. This should - * be part of the audio driver. - */ - alchemy_gpio_direction_output(209, 1); - - pm_power_off = mirage_power_off; - _machine_halt = mirage_power_off; - _machine_restart = (void(*)(char *))mips_softreset; - } -#endif - -#ifdef CONFIG_MIPS_BOSPORUS - pm_power_off = bosporus_power_off; - _machine_halt = bosporus_power_off; - _machine_restart = (void(*)(char *))mips_softreset; -#endif - au_sync(); -} - -static int __init db1x00_init_irq(void) -{ -#if defined(CONFIG_MIPS_MIRAGE) - irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ -#elif defined(CONFIG_MIPS_DB1550) - irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#elif defined(CONFIG_MIPS_DB1500) - irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#elif defined(CONFIG_MIPS_DB1100) - irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#elif defined(CONFIG_MIPS_DB1000) - irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ - irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ - irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ - irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ - irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ -#endif - return 0; -} -arch_initcall(db1x00_init_irq); diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c deleted file mode 100644 index 9e6b3d442ac..00000000000 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * DBAu1xxx board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1000_dma.h> -#include <asm/mach-db1x00/bcsr.h> -#include "../platform.h" - -struct pci_dev; - -/* DB1xxx PCMCIA interrupt sources: - * CD0/1 GPIO0/3 - * STSCHG0/1 GPIO1/4 - * CARD0/1 GPIO2/5 - * Db1550: 0/1, 21/22, 3/5 - */ - -#define DB1XXX_HAS_PCMCIA -#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) - -#if defined(CONFIG_MIPS_DB1000) -#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#elif defined(CONFIG_MIPS_DB1100) -#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#elif defined(CONFIG_MIPS_DB1500) -#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#elif defined(CONFIG_MIPS_DB1550) -#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT -#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT -#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT -#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#else -/* other board: no PCMCIA */ -#undef DB1XXX_HAS_PCMCIA -#undef F_SWAPPED -#define F_SWAPPED 0 -#if defined(CONFIG_MIPS_BOSPORUS) -#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#elif defined(CONFIG_MIPS_MIRAGE) -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif -#endif - -#ifdef CONFIG_PCI -#ifdef CONFIG_MIPS_DB1500 -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 12) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} -#endif - -#ifdef CONFIG_MIPS_DB1550 -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 11) || (slot > 13) || pin == 0) - return -1; - if (slot == 11) - return (pin == 1) ? AU1550_PCI_INTC : 0xff; - if (slot == 12) { - switch (pin) { - case 1: return AU1550_PCI_INTB; - case 2: return AU1550_PCI_INTC; - case 3: return AU1550_PCI_INTD; - case 4: return AU1550_PCI_INTA; - } - } - if (slot == 13) { - switch (pin) { - case 1: return AU1550_PCI_INTA; - case 2: return AU1550_PCI_INTB; - case 3: return AU1550_PCI_INTC; - case 4: return AU1550_PCI_INTD; - } - } - return -1; -} -#endif - -#ifdef CONFIG_MIPS_BOSPORUS -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 11) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 11) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - default: return 0xff; - } - } - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} -#endif - -#ifdef CONFIG_MIPS_MIRAGE -static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 11) || (slot > 13) || pin == 0) - return -1; - if (slot == 11) - return (pin == 1) ? AU1500_PCI_INTD : 0xff; - if (slot == 12) - return (pin == 3) ? AU1500_PCI_INTC : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - default: return 0xff; - } - } - return -1; -} -#endif - -static struct resource alchemy_pci_host_res[] = { - [0] = { - .start = AU1500_PCI_PHYS_ADDR, - .end = AU1500_PCI_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct alchemy_pci_platdata db1xxx_pci_pd = { - .board_map_irq = db1xxx_map_pci_irq, -}; - -static struct platform_device db1xxx_pci_host_dev = { - .dev.platform_data = &db1xxx_pci_pd, - .name = "alchemy-pci", - .id = 0, - .num_resources = ARRAY_SIZE(alchemy_pci_host_res), - .resource = alchemy_pci_host_res, -}; - -static int __init db15x0_pci_init(void) -{ - return platform_device_register(&db1xxx_pci_host_dev); -} -/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ -arch_initcall(db15x0_pci_init); -#endif - -#ifdef CONFIG_MIPS_DB1100 -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; -#endif - -static struct resource alchemy_ac97c_res[] = { - [0] = { - .start = AU1000_AC97_PHYS_ADDR, - .end = AU1000_AC97_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMA_ID_AC97C_TX, - .end = DMA_ID_AC97C_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMA_ID_AC97C_RX, - .end = DMA_ID_AC97C_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device alchemy_ac97c_dev = { - .name = "alchemy-ac97c", - .id = -1, - .resource = alchemy_ac97c_res, - .num_resources = ARRAY_SIZE(alchemy_ac97c_res), -}; - -static struct platform_device alchemy_ac97c_dma_dev = { - .name = "alchemy-pcm-dma", - .id = 0, -}; - -static struct platform_device db1x00_codec_dev = { - .name = "ac97-codec", - .id = -1, -}; - -static struct platform_device db1x00_audio_dev = { - .name = "db1000-audio", -}; - -static int __init db1xxx_dev_init(void) -{ -#ifdef DB1XXX_HAS_PCMCIA - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0, - /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, - /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); -#endif -#ifdef CONFIG_MIPS_DB1100 - platform_device_register(&au1100_lcd_device); -#endif - db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); - - platform_device_register(&db1x00_codec_dev); - platform_device_register(&alchemy_ac97c_dma_dev); - platform_device_register(&alchemy_ac97c_dev); - platform_device_register(&db1x00_audio_dev); - - return 0; -} -device_initcall(db1xxx_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile deleted file mode 100644 index 97c6615ba2b..00000000000 --- a/arch/mips/alchemy/devboards/pb1000/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for the Alchemy Semiconductor Pb1000 board. -# - -obj-y := board_setup.o diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c deleted file mode 100644 index e64fdcbf75d..00000000000 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/pm.h> -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-pb1x00/pb1000.h> -#include <asm/reboot.h> -#include <prom.h> - -#include "../platform.h" - -const char *get_system_type(void) -{ - return "Alchemy Pb1000"; -} - -static void board_reset(char *c) -{ - asm volatile ("jr %0" : : "r" (0xbfc00000)); -} - -static void board_power_off(void) -{ - while (1) - asm volatile ( - " .set mips32 \n" - " wait \n" - " .set mips0 \n"); -} - -void __init board_setup(void) -{ - u32 pin_func, static_cfg0; - u32 sys_freqctrl, sys_clksrc; - u32 prid = read_c0_prid(); - - sys_freqctrl = 0; - sys_clksrc = 0; - - /* Set AUX clock to 12 MHz * 8 = 96 MHz */ - au_writel(8, SYS_AUXPLL); - alchemy_gpio1_input_enable(); - udelay(100); - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* Zero and disable FREQ2 */ - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* Zero and disable USBH/USBD clocks */ - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | - SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - au_writel(sys_clksrc, SYS_CLKSRC); - - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | - SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); - - switch (prid & 0x000000FF) { - case 0x00: /* DA */ - case 0x01: /* HA */ - case 0x02: /* HB */ - /* CPU core freq to 48 MHz to slow it way down... */ - au_writel(4, SYS_CPUPLL); - - /* - * Setup 48 MHz FREQ2 from CPUPLL for USB Host - * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz - */ - sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* CPU core freq to 384 MHz */ - au_writel(0x20, SYS_CPUPLL); - - printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n"); - break; - - default: /* HC and newer */ - /* FREQ2 = aux / 2 = 48 MHz */ - sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | - SYS_FC_FE2 | SYS_FC_FS2; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - break; - } - - /* - * Route 48 MHz FREQ2 into USB Host and/or Device - */ - sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT; - au_writel(sys_clksrc, SYS_CLKSRC); - - /* Configure pins GPIO[14:9] as GPIO */ - pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB); - - /* 2nd USB port is USB host */ - pin_func |= SYS_PF_USB; - - au_writel(pin_func, SYS_PINFUNC); - - alchemy_gpio_direction_input(11); - alchemy_gpio_direction_input(13); - alchemy_gpio_direction_output(4, 0); - alchemy_gpio_direction_output(5, 0); -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ - - /* Make GPIO 15 an input (for interrupt line) */ - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF; - /* We don't need I2S, so make it available for GPIO[31:29] */ - pin_func |= SYS_PF_I2S; - au_writel(pin_func, SYS_PINFUNC); - - alchemy_gpio_direction_input(15); - - static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00; - au_writel(static_cfg0, MEM_STCFG0); - - /* configure RCE2* for LCD */ - au_writel(0x00000004, MEM_STCFG2); - - /* MEM_STTIME2 */ - au_writel(0x09000000, MEM_STTIME2); - - /* Set 32-bit base address decoding for RCE2* */ - au_writel(0x10003ff0, MEM_STADDR2); - - /* - * PCI CPLD setup - * Expand CE0 to cover PCI - */ - au_writel(0x11803e40, MEM_STADDR1); - - /* Burst visibility on */ - au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); - - au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */ - au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */ - - /* Setup the static bus controller */ - au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ - au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ - au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ - - /* - * Enable Au1000 BCLK switching - note: sed1356 must not use - * its BCLK (Au1000 LCLK) for any timings - */ - switch (prid & 0x000000FF) { - case 0x00: /* DA */ - case 0x01: /* HA */ - case 0x02: /* HB */ - break; - default: /* HC and newer */ - /* - * Enable sys bus clock divider when IDLE state or no bus - * activity. - */ - au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); - break; - } - - pm_power_off = board_power_off; - _machine_halt = board_power_off; - _machine_restart = board_reset; -} - -static int __init pb1000_init_irq(void) -{ - irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); - return 0; -} -arch_initcall(pb1000_init_irq); - -static int __init pb1000_device_init(void) -{ - return db1x_register_norflash(8 * 1024 * 1024, 4, 0); -} -device_initcall(pb1000_device_init); diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100.c index d108fd573aa..cff50d05ddd 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100.c @@ -1,42 +1,37 @@ /* - * Copyright 2002, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> + * Pb1100 board platform device registration * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2009 Manuel Lauss * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/delay.h> #include <linux/gpio.h> #include <linux/init.h> -#include <linux/delay.h> #include <linux/interrupt.h> - +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-db1x00/bcsr.h> - #include <prom.h> - +#include "platform.h" const char *get_system_type(void) { - return "Alchemy Pb1100"; + return "PB1100"; } void __init board_setup(void) @@ -115,13 +110,58 @@ void __init board_setup(void) } } -static int __init pb1100_init_irq(void) +/******************************************************************************/ + +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; + +static int __init pb1100_dev_init(void) { + int swapped; + irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ + /* PCMCIA. single socket, identical to Pb1500 */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ + /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&au1100_lcd_device); + return 0; } -arch_initcall(pb1100_init_irq); +device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile deleted file mode 100644 index 7e3756c83fe..00000000000 --- a/arch/mips/alchemy/devboards/pb1100/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2001, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for the Alchemy Semiconductor Pb1100 board. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c deleted file mode 100644 index 9c57c01a68c..00000000000 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Pb1100 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/init.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-db1x00/bcsr.h> - -#include "../platform.h" - -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; - -static int __init pb1100_dev_init(void) -{ - int swapped; - - /* PCMCIA. single socket, identical to Pb1500 */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */ - /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; - db1x_register_norflash(64 * 1024 * 1024, 4, swapped); - platform_device_register(&au1100_lcd_device); - - return 0; -} -device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile deleted file mode 100644 index 18c1bd53e4c..00000000000 --- a/arch/mips/alchemy/devboards/pb1200/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c deleted file mode 100644 index 6d06b07c238..00000000000 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Alchemy Pb1200/Db1200 board setup. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/sched.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-db1x00/bcsr.h> - -#ifdef CONFIG_MIPS_PB1200 -#include <asm/mach-pb1x00/pb1200.h> -#endif - -#ifdef CONFIG_MIPS_DB1200 -#include <asm/mach-db1x00/db1200.h> -#define PB1200_INT_BEGIN DB1200_INT_BEGIN -#define PB1200_INT_END DB1200_INT_END -#endif - -#include <prom.h> - -const char *get_system_type(void) -{ - return "Alchemy Pb1200"; -} - -void __init board_setup(void) -{ - printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); - bcsr_init(PB1200_BCSR_PHYS_ADDR, - PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); - -#if 0 - { - u32 pin_func; - - /* - * Enable PSC1 SYNC for AC97. Normaly done in audio driver, - * but it is board specific code, so put it here. - */ - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; - au_writel(pin_func, SYS_PINFUNC); - - au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ - au_sync(); - } -#endif - -#if defined(CONFIG_I2C_AU1550) - { - u32 freq0, clksrc; - u32 pin_func; - - /* Select SMBus in CPLD */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); - - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); - /* Set GPIOs correctly */ - pin_func |= 2 << 17; - au_writel(pin_func, SYS_PINFUNC); - au_sync(); - - /* The I2C driver depends on 50 MHz clock */ - freq0 = au_readl(SYS_FREQCTRL0); - au_sync(); - freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); - freq0 |= 3 << SYS_FC_FRDIV1_BIT; - /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ - au_writel(freq0, SYS_FREQCTRL0); - au_sync(); - freq0 |= SYS_FC_FE1; - au_writel(freq0, SYS_FREQCTRL0); - au_sync(); - - clksrc = au_readl(SYS_CLKSRC); - au_sync(); - clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); - /* Bit 22 is EXTCLK0 for PSC0 */ - clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; - au_writel(clksrc, SYS_CLKSRC); - au_sync(); - } -#endif - - /* - * The Pb1200 development board uses external MUX for PSC0 to - * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI - */ -#ifdef CONFIG_I2C_AU1550 - bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); -#endif - au_sync(); -} - -static int __init pb1200_init_irq(void) -{ - /* We have a problem with CPLD rev 3. */ - if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n"); - printk(KERN_ERR "updated to latest revision. This software will\n"); - printk(KERN_ERR "not work on anything less than CPLD rev 4.\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - printk(KERN_ERR "WARNING!!!\n"); - panic("Game over. Your score is 0."); - } - - irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); - bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); - - return 0; -} -arch_initcall(pb1200_init_irq); - - -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ - return 0; -} diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c deleted file mode 100644 index 54f7f7b0676..00000000000 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Pb1200/DBAu1200 board platform device registration - * - * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/dma-mapping.h> -#include <linux/init.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/smc91x.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1100_mmc.h> -#include <asm/mach-au1x00/au1xxx_dbdma.h> -#include <asm/mach-db1x00/bcsr.h> -#include <asm/mach-pb1x00/pb1200.h> - -#include "../platform.h" - -static int mmc_activity; - -static void pb1200mmc0_set_power(void *mmc_host, int state) -{ - if (state) - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); - else - bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); - - msleep(1); -} - -static int pb1200mmc0_card_readonly(void *mmc_host) -{ - return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; -} - -static int pb1200mmc0_card_inserted(void *mmc_host) -{ - return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; -} - -static void pb1200_mmcled_set(struct led_classdev *led, - enum led_brightness brightness) -{ - if (brightness != LED_OFF) { - if (++mmc_activity == 1) - bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); - } else { - if (--mmc_activity == 0) - bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); - } -} - -static struct led_classdev pb1200mmc_led = { - .brightness_set = pb1200_mmcled_set, -}; - -static void pb1200mmc1_set_power(void *mmc_host, int state) -{ - if (state) - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); - else - bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); - - msleep(1); -} - -static int pb1200mmc1_card_readonly(void *mmc_host) -{ - return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; -} - -static int pb1200mmc1_card_inserted(void *mmc_host) -{ - return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; -} - -static struct au1xmmc_platform_data pb1200mmc_platdata[2] = { - [0] = { - .set_power = pb1200mmc0_set_power, - .card_inserted = pb1200mmc0_card_inserted, - .card_readonly = pb1200mmc0_card_readonly, - .cd_setup = NULL, /* use poll-timer in driver */ - .led = &pb1200mmc_led, - }, - [1] = { - .set_power = pb1200mmc1_set_power, - .card_inserted = pb1200mmc1_card_inserted, - .card_readonly = pb1200mmc1_card_readonly, - .cd_setup = NULL, /* use poll-timer in driver */ - .led = &pb1200mmc_led, - }, -}; - -static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); - -static struct resource au1200_mmc0_res[] = { - [0] = { - .start = AU1100_SD0_PHYS_ADDR, - .end = AU1100_SD0_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX0, - .end = AU1200_DSCR_CMD0_SDMS_TX0, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX0, - .end = AU1200_DSCR_CMD0_SDMS_RX0, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device pb1200_mmc0_dev = { - .name = "au1xxx-mmc", - .id = 0, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &pb1200mmc_platdata[0], - }, - .num_resources = ARRAY_SIZE(au1200_mmc0_res), - .resource = au1200_mmc0_res, -}; - -static struct resource au1200_mmc1_res[] = { - [0] = { - .start = AU1100_SD1_PHYS_ADDR, - .end = AU1100_SD1_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_SDMS_TX1, - .end = AU1200_DSCR_CMD0_SDMS_TX1, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_SDMS_RX1, - .end = AU1200_DSCR_CMD0_SDMS_RX1, - .flags = IORESOURCE_DMA, - } -}; - -static struct platform_device pb1200_mmc1_dev = { - .name = "au1xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &pb1200mmc_platdata[1], - }, - .num_resources = ARRAY_SIZE(au1200_mmc1_res), - .resource = au1200_mmc1_res, -}; - - -static struct resource ide_resources[] = { - [0] = { - .start = IDE_PHYS_ADDR, - .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = IDE_INT, - .end = IDE_INT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = AU1200_DSCR_CMD0_DMA_REQ1, - .end = AU1200_DSCR_CMD0_DMA_REQ1, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 ide_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ide_device = { - .name = "au1200-ide", - .id = 0, - .dev = { - .dma_mask = &ide_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(ide_resources), - .resource = ide_resources -}; - -static struct smc91x_platdata smc_data = { - .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91c111_resources[] = { - [0] = { - .name = "smc91x-regs", - .start = SMC91C111_PHYS_ADDR, - .end = SMC91C111_PHYS_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = SMC91C111_INT, - .end = SMC91C111_INT, - .flags = IORESOURCE_IRQ - }, -}; - -static struct platform_device smc91c111_device = { - .dev = { - .platform_data = &smc_data, - }, - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(smc91c111_resources), - .resource = smc91c111_resources -}; - -static struct resource au1200_psc0_res[] = { - [0] = { - .start = AU1550_PSC0_PHYS_ADDR, - .end = AU1550_PSC0_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_PSC0_INT, - .end = AU1200_PSC0_INT, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = AU1200_DSCR_CMD0_PSC0_TX, - .end = AU1200_DSCR_CMD0_PSC0_TX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = AU1200_DSCR_CMD0_PSC0_RX, - .end = AU1200_DSCR_CMD0_PSC0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device pb1200_i2c_dev = { - .name = "au1xpsc_smbus", - .id = 0, /* bus number */ - .num_resources = ARRAY_SIZE(au1200_psc0_res), - .resource = au1200_psc0_res, -}; - -static struct resource au1200_lcd_res[] = { - [0] = { - .start = AU1200_LCD_PHYS_ADDR, - .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1200_LCD_INT, - .end = AU1200_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1200_lcd_dev = { - .name = "au1200-lcd", - .id = 0, - .dev = { - .dma_mask = &au1200_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1200_lcd_res), - .resource = au1200_lcd_res, -}; - -static struct platform_device *board_platform_devices[] __initdata = { - &ide_device, - &smc91c111_device, - &pb1200_i2c_dev, - &pb1200_mmc0_dev, - &pb1200_mmc1_dev, - &au1200_lcd_dev, -}; - -static int __init board_register_devices(void) -{ - int swapped; - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - PB1200_PC0_INT, PB1200_PC0_INSERT_INT, - /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, - PB1200_PC1_INT, PB1200_PC1_INSERT_INT, - /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1); - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; - db1x_register_norflash(128 * 1024 * 1024, 2, swapped); - - return platform_add_devices(board_platform_devices, - ARRAY_SIZE(board_platform_devices)); -} -device_initcall(board_register_devices); diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500.c index 37c1883b5ea..e7b807b3ec5 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500.c @@ -1,41 +1,37 @@ /* - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> + * Pb1500 board support. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Copyright (C) 2009 Manuel Lauss * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <linux/delay.h> +#include <linux/dma-mapping.h> #include <linux/gpio.h> #include <linux/init.h> #include <linux/interrupt.h> - +#include <linux/platform_device.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-db1x00/bcsr.h> - #include <prom.h> +#include "platform.h" const char *get_system_type(void) { - return "Alchemy Pb1500"; + return "PB1500"; } void __init board_setup(void) @@ -123,17 +119,80 @@ void __init board_setup(void) } } -static int __init pb1500_init_irq(void) +/******************************************************************************/ + +static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { - irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ - irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ - irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata pb1500_pci_pd = { + .board_map_irq = pb1500_map_pci_irq, + .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | + PCI_CONFIG_CH | +#if defined(__MIPSEB__) + PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, +#else + 0, +#endif +}; + +static struct platform_device pb1500_pci_host = { + .dev.platform_data = &pb1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init pb1500_dev_init(void) +{ + int swapped; + + irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ + irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ + irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); + /* PCMCIA. single socket, identical to Pb1100 */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ + /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 4, swapped); + platform_device_register(&pb1500_pci_host); + return 0; } -arch_initcall(pb1500_init_irq); +arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile deleted file mode 100644 index e83b151b5b6..00000000000 --- a/arch/mips/alchemy/devboards/pb1500/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2001, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for the Alchemy Semiconductor Pb1500 board. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c deleted file mode 100644 index 1e52a01bac0..00000000000 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Pb1500 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/dma-mapping.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-db1x00/bcsr.h> - -#include "../platform.h" - -static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 12) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} - -static struct resource alchemy_pci_host_res[] = { - [0] = { - .start = AU1500_PCI_PHYS_ADDR, - .end = AU1500_PCI_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct alchemy_pci_platdata pb1500_pci_pd = { - .board_map_irq = pb1500_map_pci_irq, - .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H | - PCI_CONFIG_CH | -#if defined(__MIPSEB__) - PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM, -#else - 0, -#endif -}; - -static struct platform_device pb1500_pci_host = { - .dev.platform_data = &pb1500_pci_pd, - .name = "alchemy-pci", - .id = 0, - .num_resources = ARRAY_SIZE(alchemy_pci_host_res), - .resource = alchemy_pci_host_res, -}; - -static int __init pb1500_dev_init(void) -{ - int swapped; - - /* PCMCIA. single socket, identical to Pb1100 */ - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */ - /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */ - - swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; - db1x_register_norflash(64 * 1024 * 1024, 4, swapped); - platform_device_register(&pb1500_pci_host); - - return 0; -} -arch_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550.c index a4604b8a349..b37e7de8d92 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550.c @@ -1,7 +1,7 @@ /* - * Pb1550 board platform device registration + * Pb1550 board support. * - * Copyright (C) 2009 Manuel Lauss + * Copyright (C) 2009-2011 Manuel Lauss * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,13 +20,44 @@ #include <linux/dma-mapping.h> #include <linux/init.h> +#include <linux/interrupt.h> #include <linux/platform_device.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1xxx_dbdma.h> -#include <asm/mach-pb1x00/pb1550.h> +#include <asm/mach-au1x00/au1550nd.h> +#include <asm/mach-au1x00/gpio.h> #include <asm/mach-db1x00/bcsr.h> +#include "platform.h" -#include "../platform.h" +const char *get_system_type(void) +{ + return "PB1550"; +} + +void __init board_setup(void) +{ + u32 pin_func; + + bcsr_init(PB1550_BCSR_PHYS_ADDR, + PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); + + alchemy_gpio2_enable(); + + /* + * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, + * but it is board specific code, so put it here. + */ + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; + au_writel(pin_func, SYS_PINFUNC); + + bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ + + printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); +} + +/******************************************************************************/ static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) { @@ -101,10 +132,79 @@ static struct platform_device pb1550_i2c_dev = { .resource = au1550_psc2_res, }; +static struct mtd_partition pb1550_nand_parts[] = { + [0] = { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + [1] = { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct au1550nd_platdata pb1550_nand_pd = { + .parts = pb1550_nand_parts, + .num_parts = ARRAY_SIZE(pb1550_nand_parts), + .devwidth = 0, /* x8 NAND default, needs fixing up */ +}; + +static struct resource pb1550_nand_res[] = { + [0] = { + .start = 0x20000000, + .end = 0x20000fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device pb1550_nand_dev = { + .name = "au1550-nand", + .id = -1, + .resource = pb1550_nand_res, + .num_resources = ARRAY_SIZE(pb1550_nand_res), + .dev = { + .platform_data = &pb1550_nand_pd, + }, +}; + +static void __init pb1550_nand_setup(void) +{ + int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | + ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); + + switch (boot_swapboot) { + case 0: + case 2: + case 8: + case 0xC: + case 0xD: + /* x16 NAND Flash */ + pb1550_nand_pd.devwidth = 1; + /* fallthrough */ + case 1: + case 9: + case 3: + case 0xE: + case 0xF: + /* x8 NAND, already set up */ + platform_device_register(&pb1550_nand_dev); + } +} + static int __init pb1550_dev_init(void) { int swapped; + irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); + irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); + + /* enable both PCMCIA card irqs in the shared line */ + alchemy_gpio2_enable_int(201); + alchemy_gpio2_enable_int(202); + /* Pb1550, like all others, also has statuschange irqs; however they're * wired up on one of the Au1550's shared GPIO201_205 line, which also * services the PCMCIA card interrupts. So we ignore statuschange and @@ -130,6 +230,10 @@ static int __init pb1550_dev_init(void) AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); + /* NAND setup */ + gpio_direction_input(206); /* GPIO206 high */ + pb1550_nand_setup(); + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; db1x_register_norflash(128 * 1024 * 1024, 4, swapped); platform_device_register(&pb1550_pci_host); diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile deleted file mode 100644 index 9661b6ec5dd..00000000000 --- a/arch/mips/alchemy/devboards/pb1550/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2000, 2008 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for the Alchemy Semiconductor Pb1550 board. -# - -obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c deleted file mode 100644 index 0f62d1e3df2..00000000000 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Alchemy Pb1550 board setup. - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-pb1x00/pb1550.h> -#include <asm/mach-db1x00/bcsr.h> -#include <asm/mach-au1x00/gpio.h> - -#include <prom.h> - -const char *get_system_type(void) -{ - return "Alchemy Pb1550"; -} - -void __init board_setup(void) -{ - u32 pin_func; - - bcsr_init(PB1550_BCSR_PHYS_ADDR, - PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); - - alchemy_gpio2_enable(); - - /* - * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, - * but it is board specific code, so put it here. - */ - pin_func = au_readl(SYS_PINFUNC); - au_sync(); - pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; - au_writel(pin_func, SYS_PINFUNC); - - bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ - - printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); -} - -static int __init pb1550_init_irq(void) -{ - irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); - - /* enable both PCMCIA card irqs in the shared line */ - alchemy_gpio2_enable_int(201); - alchemy_gpio2_enable_int(202); - - return 0; -} -arch_initcall(pb1550_init_irq); diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c index 49a4b3244d8..621f70afb63 100644 --- a/arch/mips/alchemy/devboards/platform.c +++ b/arch/mips/alchemy/devboards/platform.c @@ -13,6 +13,13 @@ #include <asm/reboot.h> #include <asm/mach-db1x00/bcsr.h> + +static struct platform_device db1x00_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + + static void db1x_power_off(void) { bcsr_write(BCSR_RESETS, 0); @@ -25,7 +32,7 @@ static void db1x_reset(char *c) bcsr_write(BCSR_SYSTEM, 0); } -static int __init db1x_poweroff_setup(void) +static int __init db1x_late_setup(void) { if (!pm_power_off) pm_power_off = db1x_power_off; @@ -34,9 +41,11 @@ static int __init db1x_poweroff_setup(void) if (!_machine_restart) _machine_restart = db1x_reset; + platform_device_register(&db1x00_rtc_dev); + return 0; } -late_initcall(db1x_poweroff_setup); +device_initcall(db1x_late_setup); /* register a pcmcia socket */ int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start, diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index e5306b56da6..93a22107cc4 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -33,10 +33,9 @@ #include <asm/mach-au1x00/au1000.h> #include <prom.h> -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ - defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) +#if defined(CONFIG_MIPS_DB1000) || \ + defined(CONFIG_MIPS_PB1100) || \ + defined(CONFIG_MIPS_PB1500) #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 #else /* Au1550/Au1200-based develboards */ @@ -62,5 +61,9 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile deleted file mode 100644 index cb73fe256dc..00000000000 --- a/arch/mips/alchemy/gpr/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2003 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for Trapeze ITS GPR board. -# - -obj-y += board_setup.o init.o platform.o diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c deleted file mode 100644 index dea45c78fdc..00000000000 --- a/arch/mips/alchemy/gpr/board_setup.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2010 Wolfgang Grandegger <wg@denx.de> - * - * Copyright 2000-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/pm.h> - -#include <asm/reboot.h> -#include <asm/mach-au1x00/au1000.h> - -#include <prom.h> - -static void gpr_reset(char *c) -{ - /* switch System-LED to orange (red# and green# on) */ - alchemy_gpio_direction_output(4, 0); - alchemy_gpio_direction_output(5, 0); - - /* trigger watchdog to reset board in 200ms */ - printk(KERN_EMERG "Triggering watchdog soft reset...\n"); - raw_local_irq_disable(); - alchemy_gpio_direction_output(1, 0); - udelay(1); - alchemy_gpio_set_value(1, 1); - while (1) - cpu_wait(); -} - -static void gpr_power_off(void) -{ - while (1) - cpu_wait(); -} - -void __init board_setup(void) -{ - printk(KERN_INFO "Trapeze ITS GPR board\n"); - - pm_power_off = gpr_power_off; - _machine_halt = gpr_power_off; - _machine_restart = gpr_reset; - - /* Enable UART1/3 */ - alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); - alchemy_uart_enable(AU1000_UART1_PHYS_ADDR); - - /* Take away Reset of UMTS-card */ - alchemy_gpio_direction_output(215, 1); -} diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c deleted file mode 100644 index 229aafae680..00000000000 --- a/arch/mips/alchemy/gpr/init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2010 Wolfgang Grandegger <wg@denx.de> - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/init.h> -#include <linux/kernel.h> - -#include <asm/bootinfo.h> -#include <asm/mach-au1x00/au1000.h> - -#include <prom.h> - -const char *get_system_type(void) -{ - return "GPR"; -} - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -} diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile deleted file mode 100644 index 81b540ceaf8..00000000000 --- a/arch/mips/alchemy/mtx-1/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2003 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# Bruno Randolf <bruno.randolf@4g-systems.biz> -# -# Makefile for 4G Systems MTX-1 board. -# - -obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c deleted file mode 100644 index 851a5ab4c8f..00000000000 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * 4G Systems MTX-1 board setup. - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * Bruno Randolf <bruno.randolf@4g-systems.biz> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/pm.h> - -#include <asm/reboot.h> -#include <asm/mach-au1x00/au1000.h> - -#include <prom.h> - -static void mtx1_reset(char *c) -{ - /* Jump to the reset vector */ - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -static void mtx1_power_off(void) -{ - while (1) - asm volatile ( - " .set mips32 \n" - " wait \n" - " .set mips0 \n"); -} - -void __init board_setup(void) -{ -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* Enable USB power switch */ - alchemy_gpio_direction_output(204, 0); -#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ - - /* Initialize sys_pinfunc */ - au_writel(SYS_PF_NI2, SYS_PINFUNC); - - /* Initialize GPIO */ - au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); - alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ - alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ - alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ - alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ - - /* Enable LED and set it to green */ - alchemy_gpio_direction_output(211, 1); /* green on */ - alchemy_gpio_direction_output(212, 0); /* red off */ - - pm_power_off = mtx1_power_off; - _machine_halt = mtx1_power_off; - _machine_restart = mtx1_reset; - - printk(KERN_INFO "4G Systems MTX-1 Board\n"); -} - -static int __init mtx1_init_irq(void) -{ - irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); - - return 0; -} -arch_initcall(mtx1_init_irq); diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c deleted file mode 100644 index 2e81cc7f342..00000000000 --- a/arch/mips/alchemy/mtx-1/init.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * 4G Systems MTX-1 board setup - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * Bruno Randolf <bruno.randolf@4g-systems.biz> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/bootinfo.h> -#include <asm/mach-au1x00/au1000.h> - -#include <prom.h> - -const char *get_system_type(void) -{ - return "MTX-1"; -} - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - - memsize_str = prom_getenv("memsize"); - if (!memsize_str) - memsize = 0x04000000; - else - strict_strtoul(memsize_str, 0, &memsize); - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -} diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile deleted file mode 100644 index 91defcf4f33..00000000000 --- a/arch/mips/alchemy/xxs1500/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2003 MontaVista Software Inc. -# Author: MontaVista Software, Inc. <source@mvista.com> -# -# Makefile for MyCable XXS1500 board. -# - -obj-y += init.o board_setup.o platform.o diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c deleted file mode 100644 index 3fa83f72e01..00000000000 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2000-2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/pm.h> - -#include <asm/reboot.h> -#include <asm/mach-au1x00/au1000.h> - -#include <prom.h> - -static void xxs1500_reset(char *c) -{ - /* Jump to the reset vector */ - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -static void xxs1500_power_off(void) -{ - while (1) - asm volatile ( - " .set mips32 \n" - " wait \n" - " .set mips0 \n"); -} - -void __init board_setup(void) -{ - u32 pin_func; - - pm_power_off = xxs1500_power_off; - _machine_halt = xxs1500_power_off; - _machine_restart = xxs1500_reset; - - alchemy_gpio1_input_enable(); - alchemy_gpio2_enable(); - - /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ - pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; - pin_func |= SYS_PF_UR3; - au_writel(pin_func, SYS_PINFUNC); - - /* Enable UART */ - alchemy_uart_enable(AU1000_UART3_PHYS_ADDR); - /* Enable DTR (MCR bit 0) = USB power up */ - __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); - wmb(); -} - -static int __init xxs1500_init_irq(void) -{ - irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); - irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); - - irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); - irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ - irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); - - return 0; -} -arch_initcall(xxs1500_init_irq); diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c deleted file mode 100644 index 0ee02cfa989..00000000000 --- a/arch/mips/alchemy/xxs1500/init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * XXS1500 board setup - * - * Copyright 2003, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/init.h> -#include <linux/kernel.h> - -#include <asm/bootinfo.h> -#include <asm/mach-au1x00/au1000.h> - -#include <prom.h> - -const char *get_system_type(void) -{ - return "XXS1500"; -} - -void __init prom_init(void) -{ - unsigned char *memsize_str; - unsigned long memsize; - - prom_argc = fw_arg0; - prom_argv = (char **)fw_arg1; - prom_envp = (char **)fw_arg2; - - prom_init_cmdline(); - - memsize_str = prom_getenv("memsize"); - if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize)) - memsize = 0x04000000; - - add_memory_region(0, memsize, BOOT_MEM_RAM); -} - -void prom_putchar(unsigned char c) -{ - alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); -} diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c deleted file mode 100644 index 06a3a459b8a..00000000000 --- a/arch/mips/alchemy/xxs1500/platform.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * XXS1500 board platform device registration - * - * Copyright (C) 2009 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <asm/mach-au1x00/au1000.h> - -static struct resource xxs1500_pcmcia_res[] = { - { - .name = "pcmcia-io", - .flags = IORESOURCE_MEM, - .start = AU1000_PCMCIA_IO_PHYS_ADDR, - .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, - }, - { - .name = "pcmcia-attr", - .flags = IORESOURCE_MEM, - .start = AU1000_PCMCIA_ATTR_PHYS_ADDR, - .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - }, - { - .name = "pcmcia-mem", - .flags = IORESOURCE_MEM, - .start = AU1000_PCMCIA_MEM_PHYS_ADDR, - .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - }, -}; - -static struct platform_device xxs1500_pcmcia_dev = { - .name = "xxs1500_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res), - .resource = xxs1500_pcmcia_res, -}; - -static struct platform_device *xxs1500_devs[] __initdata = { - &xxs1500_pcmcia_dev, -}; - -static int __init xxs1500_dev_init(void) -{ - return platform_add_devices(xxs1500_devs, - ARRAY_SIZE(xxs1500_devs)); -} -device_initcall(xxs1500_dev_init); diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index eb063e6dead..3112df8f90d 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -2,6 +2,9 @@ void putc(char c) { - /* all current (Jan. 2010) in-kernel boards */ +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 4044c9e0fb7..17a36c12517 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -1,118 +1,359 @@ +CONFIG_MIPS=y CONFIG_MIPS_ALCHEMY=y +CONFIG_MIPS_DB1000=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1000" +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-db1x00" +CONFIG_LOCALVERSION_AUTO=y CONFIG_KERNEL_LZMA=y +CONFIG_DEFAULT_HOSTNAME="db1x00" +CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_AUDIT=y CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SYSCTL=y CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_SLABINFO=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_FREEZER=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y CONFIG_PM_RUNTIME=y +CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NET_IPIP=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_LRO=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_STP=y +CONFIG_GARP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_LLC=y +CONFIG_LLC2=y +CONFIG_DNS_RESOLVER=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set +CONFIG_SCSI_MOD=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_SFF=y +CONFIG_ATA_BMDMA=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_PCMCIA=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_FIREWIRE=y +CONFIG_FIREWIRE_OHCI=y +CONFIG_FIREWIRE_OHCI_DEBUG=y +CONFIG_FIREWIRE_NET=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_NET_ETHERNET=y CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=y +CONFIG_PCMCIA_PCNET=y +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOE=y +CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_DEVKMEM=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_TTY_PRINTK=y +CONFIG_DEVPORT=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_AU1100=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x16=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XAUDIO=y +CONFIG_SND_SOC_AU1XAC97C=y +CONFIG_SND_SOC_DB1000=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_USB_HID=y +CONFIG_USB_SUPPORT=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_GENERIC_ACL=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y CONFIG_TMPFS=y -CONFIG_CRAMFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y CONFIG_ROOT_NFS=y +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16" CONFIG_DEBUG_ZBOOT=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig deleted file mode 100644 index c6b49938ee8..00000000000 --- a/arch/mips/configs/db1100_defconfig +++ /dev/null @@ -1,122 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1100=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1100" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_IDE_TASK_IOCTL=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_AU1100=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig new file mode 100644 index 00000000000..c38b190151c --- /dev/null +++ b/arch/mips/configs/db1300_defconfig @@ -0,0 +1,391 @@ +CONFIG_MIPS=y +CONFIG_MIPS_ALCHEMY=y +CONFIG_ALCHEMY_GPIOINT_AU1300=y +CONFIG_MIPS_DB1300=y +CONFIG_SOC_AU1300=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +CONFIG_GENERIC_GPIO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_CPU_MIPS32_R1=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_32BIT=y +CONFIG_PAGE_SIZE_4KB=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-db1300" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_LZMA=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_TINY_RCU=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_SLAB=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_INLINE_SPIN_UNLOCK=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_MMU=y +CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_TRAD_SIGNALS=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_INET_TUNNEL=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_UB=y +CONFIG_HAVE_IDE=y +CONFIG_IDE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +CONFIG_BLK_DEV_IDECS=y +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y +CONFIG_BLK_DEV_PLATFORM=y +CONFIG_SCSI_MOD=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_SMSC_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_SMSC911X=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_WM97XX=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_SMBUS=y +CONFIG_I2C_AU1550=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_AU1550=y +CONFIG_SPI_BITBANG=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +CONFIG_SENSORS_ADM1025=y +CONFIG_FB=y +CONFIG_FB_AU1200=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_CACHE_LZO=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1300=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM9712=y +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_AU1XXX=y +CONFIG_EXT2_FS=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_GENERIC_ACL=y +CONFIG_FAT_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200" +CONFIG_DEBUG_ZBOOT=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y +CONFIG_BITREVERSE=y +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig deleted file mode 100644 index b6e21c7cb6b..00000000000 --- a/arch/mips/configs/db1500_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1500=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1500" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCI=y -CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 798a553c9e8..36cda27725e 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -1,145 +1,262 @@ +CONFIG_MIPS=y CONFIG_MIPS_ALCHEMY=y CONFIG_MIPS_DB1550=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_GPIO=y +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set +CONFIG_HZ=100 CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="-db1550" +CONFIG_LOCALVERSION_AUTO=y CONFIG_KERNEL_LZMA=y +CONFIG_DEFAULT_HOSTNAME="db1550" +CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_AUDIT=y CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PCI=y CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_MISC=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y CONFIG_PM_RUNTIME=y +CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_INET_TUNNEL=y +CONFIG_INET_LRO=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_DNS_RESOLVER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_AU1550=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_AT24=y +CONFIG_SCSI_MOD=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_ATA_SFF=y +CONFIG_ATA_BMDMA=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_PCMCIA=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_NET_ETHERNET=y CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=y +CONFIG_PCMCIA_PCNET=y +CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_DEVKMEM=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_DEVPORT=y CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_AU1550=y CONFIG_SPI=y +CONFIG_SPI_MASTER=y CONFIG_SPI_AU1550=y -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_SPI_BITBANG=y +CONFIG_HWMON=y +CONFIG_SENSORS_ADM1025=y +CONFIG_SENSORS_LM70=y +CONFIG_DUMMY_CONSOLE=y CONFIG_SOUND=y CONFIG_SND=y -CONFIG_SND_HRTIMER=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_PCI is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_PCMCIA is not set +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_AU1XPSC=y -# CONFIG_HID_SUPPORT is not set +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1200=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM9712=y +CONFIG_AC97_BUS=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y -# CONFIG_JFFS2_FS_POSIX_ACL is not set -# CONFIG_JFFS2_FS_SECURITY is not set CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y CONFIG_ROOT_NFS=y +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_852=y @@ -148,10 +265,21 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_FRAME_WARN=1024 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="noirqdebug console=ttyS0,115200 root=/dev/sda1 rootfstype=ext4" CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_BITREVERSE=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_BCH=y +CONFIG_NLATTR=y diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig deleted file mode 100644 index dcbe2704e5e..00000000000 --- a/arch/mips/configs/pb1200_defconfig +++ /dev/null @@ -1,170 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_PB1200=y -CONFIG_KSM=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-pb1200" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UB=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_BLK_DEV_IDECD=y -CONFIG_IDE_TASK_IOCTL=y -# CONFIG_IDE_PROC_FS is not set -CONFIG_BLK_DEV_IDE_AU1XXX=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_AU1550=y -CONFIG_SPI=y -CONFIG_SPI_AU1550=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_ADM1025=y -CONFIG_SENSORS_LM70=y -CONFIG_FB=y -CONFIG_FB_AU1200=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_USB is not set -# CONFIG_SND_PCMCIA is not set -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AU1XPSC=y -CONFIG_SND_SOC_DB1200=y -CONFIG_HIDRAW=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_OHCI_HCD=y -CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_AU1X=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_VFAT_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_EFI_PARTITION=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="console=ttyS0,115200" -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 2f7f41873f2..79e4a0dad0d 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -169,6 +169,7 @@ #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 +#define PRID_IMP_NETLOGIC_AU13XX 0x8000 /* * Definitions for 7:0 on legacy processors diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index de24ec57dd2..569828d3cca 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void) #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { @@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void) case 0x05030000: return ALCHEMY_CPU_AU1200; break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; } return ALCHEMY_CPU_UNKNOWN; @@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type) { switch (type) { case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1300: return 4; case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1200: @@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void); /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); +void alchemy_sleep_au1300(void); void au_sleep(void); /* USB: drivers/usb/host/alchemy-common.c */ @@ -251,6 +257,7 @@ enum alchemy_usb_block { ALCHEMY_USB_UDC0, ALCHEMY_USB_EHCI0, ALCHEMY_USB_OTG0, + ALCHEMY_USB_OHCI1, }; int alchemy_usb_control(int block, int enable); @@ -263,14 +270,92 @@ struct alchemy_pci_platdata { unsigned long pci_cfg_clr; }; -/* SOC Interrupt numbers */ +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. + */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; + +/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + +/* Au1300 allows to disconnect certain blocks from internal power supply */ +enum au1300_vss_block { + AU1300_VSS_MPE = 0, + AU1300_VSS_BSA, + AU1300_VSS_GPE, + AU1300_VSS_MGP, +}; +extern void au1300_vss_block_control(int block, int enable); + + +/* SOC Interrupt numbers */ +/* Au1000-style (IC0/1): 2 controllers with 32 sources each */ #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST +/* Au1300-style (GPIC): 1 controller with up to 128 sources */ +#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define ALCHEMY_GPIC_INT_NUM 128 +#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) + enum soc_au1000_ints { AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, @@ -591,24 +676,77 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) + +/**********************************************************************/ + /* * Physical base addresses for integrated peripherals - * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 + * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 */ #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ +#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ +#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ +#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ +#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ +#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ +#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ +#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ -#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ +#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ -#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ +#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ +#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ +#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ @@ -622,37 +760,96 @@ enum soc_au1200_ints { #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ -#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ +#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ +#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ -#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ -#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ +#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ +#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ -#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ +#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ +#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ +#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ +#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ +#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ +#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ -#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ +#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ -#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ -#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ -#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ +#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ +#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ +#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ +/**********************************************************************/ + + +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + * Registers are 128bits (0x10 bytes), divided into 4 "banks". + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ +#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +#define AU1300_GPIC_RSTVAL 0x00a0 +/* pin configuration space. one 32bit register for up to 128 IRQs */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define GPIC_GPIO_TO_BIT(gpio) \ + (1 << ((gpio) & 0x1f)) + +#define GPIC_GPIO_BANKOFF(gpio) \ + (((gpio) >> 5) * 4) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + +/***********************************************************************/ /* Au1000 SDRAM memory controller register offsets */ #define AU1000_MEM_SDMODE0 0x0000 @@ -1068,44 +1265,20 @@ enum soc_au1200_ints { #define SSI_ENABLE_CD (1 << 1) #define SSI_ENABLE_E (1 << 0) -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) -#define IR_RING_SIZE (IRDA_BASE + 0x0C) -#define IR_RING_PROMPT (IRDA_BASE + 0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) -#define IR_INT_CLEAR (IRDA_BASE + 0x18) -#define IR_CONFIG_1 (IRDA_BASE + 0x20) -# define IR_RX_INVERT_LED (1 << 0) -# define IR_TX_INVERT_LED (1 << 1) -# define IR_ST (1 << 2) -# define IR_SF (1 << 3) -# define IR_SIR (1 << 4) -# define IR_MIR (1 << 5) -# define IR_FIR (1 << 6) -# define IR_16CRC (1 << 7) -# define IR_TD (1 << 8) -# define IR_RX_ALL (1 << 9) -# define IR_DMA_ENABLE (1 << 10) -# define IR_RX_ENABLE (1 << 11) -# define IR_TX_ENABLE (1 << 12) -# define IR_LOOPBACK (1 << 14) -# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE + 0x24) -#define IR_ENABLE (IRDA_BASE + 0x28) -# define IR_RX_STATUS (1 << 9) -# define IR_TX_STATUS (1 << 10) -#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) -#define IR_CONFIG_2 (IRDA_BASE + 0x3C) -# define IR_MODE_INV (1 << 0) -# define IR_ONE_PIN (1 << 1) -#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) + +/* + * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not + * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a + * CPLD has to be told about the mode. + */ +#define AU1000_IRDA_PHY_MODE_OFF 0 +#define AU1000_IRDA_PHY_MODE_SIR 1 +#define AU1000_IRDA_PHY_MODE_FIR 2 + +struct au1k_irda_platform_data { + void(*set_phy_mode)(int mode); +}; + /* GPIO */ #define SYS_PINFUNC 0xB190002C diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index 94000a3b6f0..e221659f1bc 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -130,8 +130,10 @@ struct au1xmmc_platform_data { #define SD_CONFIG2_DF (0x00000008) #define SD_CONFIG2_DC (0x00000010) #define SD_CONFIG2_xx2 (0x000000e0) +#define SD_CONFIG2_BB (0x00000080) #define SD_CONFIG2_WB (0x00000100) #define SD_CONFIG2_RW (0x00000200) +#define SD_CONFIG2_DP (0x00000400) /* diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h new file mode 100644 index 00000000000..b3c87cc64bb --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h @@ -0,0 +1,14 @@ +/* + * platform data for au1200fb driver. + */ + +#ifndef _AU1200FB_PLAT_H_ +#define _AU1200FB_PLAT_H_ + +struct au1200fb_platdata { + int (*panel_index)(void); + int (*panel_init)(void); + int (*panel_shutdown)(void); +}; + +#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h new file mode 100644 index 00000000000..ad4c0a03afe --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h @@ -0,0 +1,16 @@ +/* + * platform data for the Au1550 NAND driver + */ + +#ifndef _AU1550ND_H_ +#define _AU1550ND_H_ + +#include <linux/mtd/partitions.h> + +struct au1550nd_platdata { + struct mtd_partition *parts; + int num_parts; + int devwidth; /* 0 = 8bit device, 1 = 16bit device */ +}; + +#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 323ce2d145f..217810e1836 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc { #define AU1200_DSCR_CMD0_PSC1_SYNC 25 #define AU1200_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UART0_TX 0 +#define AU1300_DSCR_CMD0_UART0_RX 1 +#define AU1300_DSCR_CMD0_UART1_TX 2 +#define AU1300_DSCR_CMD0_UART1_RX 3 +#define AU1300_DSCR_CMD0_UART2_TX 4 +#define AU1300_DSCR_CMD0_UART2_RX 5 +#define AU1300_DSCR_CMD0_UART3_TX 6 +#define AU1300_DSCR_CMD0_UART3_RX 7 +#define AU1300_DSCR_CMD0_SDMS_TX0 8 +#define AU1300_DSCR_CMD0_SDMS_RX0 9 +#define AU1300_DSCR_CMD0_SDMS_TX1 10 +#define AU1300_DSCR_CMD0_SDMS_RX1 11 +#define AU1300_DSCR_CMD0_AES_TX 12 +#define AU1300_DSCR_CMD0_AES_RX 13 +#define AU1300_DSCR_CMD0_PSC0_TX 14 +#define AU1300_DSCR_CMD0_PSC0_RX 15 +#define AU1300_DSCR_CMD0_PSC1_TX 16 +#define AU1300_DSCR_CMD0_PSC1_RX 17 +#define AU1300_DSCR_CMD0_PSC2_TX 18 +#define AU1300_DSCR_CMD0_PSC2_RX 19 +#define AU1300_DSCR_CMD0_PSC3_TX 20 +#define AU1300_DSCR_CMD0_PSC3_RX 21 +#define AU1300_DSCR_CMD0_LCD 22 +#define AU1300_DSCR_CMD0_NAND_FLASH 23 +#define AU1300_DSCR_CMD0_SDMS_TX2 24 +#define AU1300_DSCR_CMD0_SDMS_RX2 25 +#define AU1300_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UDMA 27 +#define AU1300_DSCR_CMD0_DMA_REQ0 28 +#define AU1300_DSCR_CMD0_DMA_REQ1 29 + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h index d5df0cab9b8..3f741af37d4 100644 --- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h @@ -13,12 +13,14 @@ #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 #define cpu_has_fpu 0 +#define cpu_has_32fpr 0 #define cpu_has_counter 1 #define cpu_has_watch 1 #define cpu_has_divec 1 #define cpu_has_vce 0 #define cpu_has_cache_cdex_p 0 #define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 #define cpu_has_mcheck 1 #define cpu_has_ejtag 1 #define cpu_has_llsc 1 @@ -29,6 +31,7 @@ #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 1 +#define cpu_has_pindexed_dcache 0 #define cpu_has_mips32r1 1 #define cpu_has_mips32r2 0 #define cpu_has_mips64r1 0 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 00000000000..556e1be20bf --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,241 @@ +/* + * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles. + * + * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com> + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include <asm/addrspace.h> +#include <asm/io.h> +#include <asm/mach-au1x00/au1000.h> + +/* with the current GPIC design, up to 128 GPIOs are possible. + * The only implementation so far is in the Au1300, which has 75 externally + * available GPIOs. + */ +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + int bit; + + gpio -= AU1300_GPIO_BASE; + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(unsigned int gpio, int v) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL + : AU1300_GPIC_PINVALCLR)); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(unsigned int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(unsigned int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(unsigned int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(unsigned int gpio) +{ + int ret; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); + break; + default: + ret = 0; + } + return ret; +} + +static inline int au1300_gpio_cansleep(unsigned int gpio) +{ + return 0; +} + +/* hardware remembers gpio 0-63 levels on powerup */ +static inline int au1300_gpio_getinitlvl(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long v; + + if (unlikely(gpio > 63)) + return 0; + else if (gpio > 31) { + gpio -= 32; + roff += 4; + } + + v = __raw_readl(roff + AU1300_GPIC_RSTVAL); + return (v >> gpio) & 1; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + +#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300 + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(unsigned int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(unsigned int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(unsigned int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned int gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int gpio) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + +#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */ + +#endif /* CONFIG GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index fcdc8c4809d..22e7ff17fc4 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -12,6 +12,7 @@ #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/gpio-au1000.h> +#include <asm/mach-au1x00/gpio-au1300.h> /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this @@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq) switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: return alchemy_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1300: + return au1300_irq_to_gpio(irq); } return -EINVAL; } diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 618d2de02ed..bb9fc23d853 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -34,6 +34,8 @@ #define PB1200_BCSR_PHYS_ADDR 0x0D800000 #define PB1200_BCSR_HEXLED_OFS 0x00400000 +#define DB1300_BCSR_PHYS_ADDR 0x19800000 +#define DB1300_BCSR_HEXLED_OFS 0x00400000 enum bcsr_id { /* BCSR base 1 */ @@ -105,6 +107,7 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, BCSR_WHOAMI_PB1200_DDR2, BCSR_WHOAMI_DB1200, + BCSR_WHOAMI_DB1300, }; /* STATUS reg. Unless otherwise noted, they're valid on all boards. @@ -118,12 +121,12 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_SRAMWIDTH 0x0080 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ #define BCSR_STATUS_SD1WP 0x0800 #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 -#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ -#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ +#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ +#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ #define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ #define BCSR_STATUS_FLASHDEN 0xC000 @@ -133,6 +136,11 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ #define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ +#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ +#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ +#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ +#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ +#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ /* DB/PB1000,1100,1500,1550 */ #define BCSR_RESETS_PHY0 0x0001 @@ -155,17 +163,17 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_GPIO200RST 0x0400 #define BCSR_BOARD_PCICLKOUT 0x0800 #define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ +#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ -/* DB/PB1200 */ +/* DB/PB1200/1300 */ #define BCSR_RESETS_ETH 0x0001 #define BCSR_RESETS_CAMERA 0x0002 #define BCSR_RESETS_DC 0x0004 #define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 /* DB1200 */ +#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ /* Not resets but in the same register */ #define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ #define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ @@ -174,13 +182,22 @@ enum bcsr_whoami_boards { #define BCSR_RESETS_SPISEL 0x4000 #define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ +#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ +#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ +#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ +#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ +#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ +#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ +#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ + #define BCSR_BOARD_LCDVEE 0x0001 #define BCSR_BOARD_LCDVDD 0x0002 #define BCSR_BOARD_LCDBL 0x0004 #define BCSR_BOARD_CAMSNAP 0x0010 #define BCSR_BOARD_CAMPWR 0x0020 #define BCSR_BOARD_SD0PWR 0x0040 - +#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ +#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ #define BCSR_SWITCHES_DIP 0x00FF #define BCSR_SWITCHES_DIP_1 0x0080 @@ -214,7 +231,10 @@ enum bcsr_whoami_boards { #define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ #define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ #define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ - +#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ +#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ +#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ +#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 7a39657108c..b2a8319521e 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -43,15 +43,20 @@ #define BCSR_INT_PC1EJECT 0x0800 #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 +#define BCSR_INT_SD1INSERT 0x4000 +#define BCSR_INT_SD1EJECT 0x8000 -#define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR +#define DB1200_IDE_PHYS_ADDR 0x18800000 #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) #define DB1200_ETH_PHYS_ADDR 0x19000300 #define DB1200_NAND_PHYS_ADDR 0x20000000 +#define PB1200_IDE_PHYS_ADDR 0x0C800000 +#define PB1200_ETH_PHYS_ADDR 0x0D000300 +#define PB1200_NAND_PHYS_ADDR 0x1C000000 + /* * External Interrupts for DBAu1200 as of 8/6/2004. * Bit positions in the CPLD registers can be calculated by taking @@ -77,6 +82,8 @@ enum external_db1200_ints { DB1200_PC1_EJECT_INT, DB1200_SD0_INSERT_INT, DB1200_SD0_EJECT_INT, + PB1200_SD1_INSERT_INT, + PB1200_SD1_EJECT_INT, DB1200_INT_END = DB1200_INT_BEGIN + 15, }; diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h new file mode 100644 index 00000000000..7fe5fb3ba87 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/db1300.h @@ -0,0 +1,40 @@ +/* + * NetLogic DB1300 board constants + */ + +#ifndef _DB1300_H_ +#define _DB1300_H_ + +/* FPGA (external mux) interrupt sources */ +#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) +#define DB1300_IDE_INT (DB1300_FIRST_INT + 0) +#define DB1300_ETH_INT (DB1300_FIRST_INT + 1) +#define DB1300_CF_INT (DB1300_FIRST_INT + 2) +#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) +#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) +#define DB1300_DC_INT (DB1300_FIRST_INT + 6) +#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) +#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) +#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) +#define DB1300_AC97_INT (DB1300_FIRST_INT + 10) +#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) +#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) +#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) +#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) +#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) +#define DB1300_LAST_INT (DB1300_FIRST_INT + 15) + +/* SMSC9210 CS */ +#define DB1300_ETH_PHYS_ADDR 0x19000000 +#define DB1300_ETH_PHYS_END 0x197fffff + +/* ATA CS */ +#define DB1300_IDE_PHYS_ADDR 0x18800000 +#define DB1300_IDE_REG_SHIFT 5 +#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) + +/* NAND CS */ +#define DB1300_NAND_PHYS_ADDR 0x20000000 +#define DB1300_NAND_PHYS_END 0x20000fff + +#endif /* _DB1300_H_ */ diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h deleted file mode 100644 index a5affb0568e..00000000000 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * AMD Alchemy DBAu1x00 Reference Boards - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_DB1X00_H -#define __ASM_DB1X00_H - -#include <asm/mach-au1x00/au1xxx_psc.h> - -#ifdef CONFIG_MIPS_DB1550 - -#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR -#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR -#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR - -#define NAND_PHYS_ADDR 0x20000000 - -#endif - -/* - * NAND defines - * - * Timing values as described in databook, * ns value stripped of the - * lower 2 bits. - * These defines are here rather than an Au1550 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) -#define NAND_CS 1 - -/* Should be done by YAMON */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ - -#endif /* __ASM_DB1X00_H */ diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h new file mode 100644 index 00000000000..15b26693238 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/irq.h @@ -0,0 +1,23 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IRQ_H +#define __ASM_MACH_GENERIC_IRQ_H + + +#ifdef NR_IRQS +#undef NR_IRQS +#endif + +#ifndef MIPS_CPU_IRQ_BASE +#define MIPS_CPU_IRQ_BASE 0 +#endif + +/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */ +#define NR_IRQS 152 + +#endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h deleted file mode 100644 index 622c58710e5..00000000000 --- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_AU1XX_MC146818RTC_H -#define __ASM_MACH_AU1XX_MC146818RTC_H - -#include <asm/io.h> -#include <asm/mach-au1x00/au1000.h> - -#define RTC_PORT(x) (0x0c000000 + (x)) -#define RTC_IRQ 8 -#define PB1500_RTC_ADDR 0x0c000000 - -static inline unsigned char CMOS_READ(unsigned long offset) -{ - offset <<= 2; - return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long offset) -{ - offset <<= 2; - au_writel(data, offset + PB1500_RTC_ADDR); -} - -#define RTC_ALWAYS_BCD 1 - -#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h deleted file mode 100644 index 65059255dc1..00000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1000.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Alchemy Semi Pb1000 Reference Board - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1000_H -#define __ASM_PB1000_H - -/* PCMCIA PB1000 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -#define PB1000_PCR 0xBE000000 -# define PCR_SLOT_0_VPP0 (1 << 0) -# define PCR_SLOT_0_VPP1 (1 << 1) -# define PCR_SLOT_0_VCC0 (1 << 2) -# define PCR_SLOT_0_VCC1 (1 << 3) -# define PCR_SLOT_0_RST (1 << 4) -# define PCR_SLOT_1_VPP0 (1 << 8) -# define PCR_SLOT_1_VPP1 (1 << 9) -# define PCR_SLOT_1_VCC0 (1 << 10) -# define PCR_SLOT_1_VCC1 (1 << 11) -# define PCR_SLOT_1_RST (1 << 12) - -#define PB1000_MDR 0xBE000004 -# define MDR_PI (1 << 5) /* PCMCIA int latch */ -# define MDR_EPI (1 << 14) /* enable PCMCIA int */ -# define MDR_CPI (1 << 15) /* clear PCMCIA int */ - -#define PB1000_ACR1 0xBE000008 -# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */ -# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */ -# define ACR1_SLOT_0_READY (1 << 2) /* ready */ -# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */ -# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */ -# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */ -# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */ -# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */ -# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */ -# define ACR1_SLOT_1_READY (1 << 10) /* ready */ -# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */ -# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */ -# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */ -# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */ - -#define CPLD_AUX0 0xBE00000C -#define CPLD_AUX1 0xBE000010 -#define CPLD_AUX2 0xBE000014 - -/* Voltage levels */ - -/* VPPEN1 - VPPEN0 */ -#define VPP_GND ((0 << 1) | (0 << 0)) -#define VPP_5V ((1 << 1) | (0 << 0)) -#define VPP_3V ((0 << 1) | (1 << 0)) -#define VPP_12V ((0 << 1) | (1 << 0)) -#define VPP_HIZ ((1 << 1) | (1 << 0)) - -/* VCCEN1 - VCCEN0 */ -#define VCC_3V ((0 << 1) | (1 << 0)) -#define VCC_5V ((1 << 1) | (0 << 0)) -#define VCC_HIZ ((0 << 1) | (0 << 0)) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -#endif /* __ASM_PB1000_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h deleted file mode 100644 index 374416adb65..00000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * AMD Alchemy Pb1200 Reference Board - * Board Registers defines. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1200_H -#define __ASM_PB1200_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the Pb1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR -#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR -/* - * AC97 and I2S are muxed on the Pb1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR - - -#define BCSR_SYSTEM_VDDI 0x001F -#define BCSR_SYSTEM_POWEROFF 0x4000 -#define BCSR_SYSTEM_RESET 0x8000 - -/* Bit positions for the different interrupt sources */ -#define BCSR_INT_IDE 0x0001 -#define BCSR_INT_ETH 0x0002 -#define BCSR_INT_PC0 0x0004 -#define BCSR_INT_PC0STSCHG 0x0008 -#define BCSR_INT_PC1 0x0010 -#define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 -#define BCSR_INT_FLASHBUSY 0x0080 -#define BCSR_INT_PC0INSERT 0x0100 -#define BCSR_INT_PC0EJECT 0x0200 -#define BCSR_INT_PC1INSERT 0x0400 -#define BCSR_INT_PC1EJECT 0x0800 -#define BCSR_INT_SD0INSERT 0x1000 -#define BCSR_INT_SD0EJECT 0x2000 -#define BCSR_INT_SD1INSERT 0x4000 -#define BCSR_INT_SD1EJECT 0x8000 - -#define SMC91C111_PHYS_ADDR 0x0D000300 -#define SMC91C111_INT PB1200_ETH_INT - -#define IDE_PHYS_ADDR 0x0C800000 -#define IDE_REG_SHIFT 5 -#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define IDE_INT PB1200_IDE_INT - -#define NAND_PHYS_ADDR 0x1C000000 - -/* - * Timing values as described in databook, * ns value stripped of - * lower 2 bits. - * These defines are here rather than an Au1200 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) - -/* - * External Interrupts for Pb1200 as of 8/6/2004. - * Bit positions in the CPLD registers can be calculated by taking - * the interrupt define and subtracting the PB1200_INT_BEGIN value. - * - * Example: IDE bis pos is = 64 - 64 - * ETH bit pos is = 65 - 64 - */ -enum external_pb1200_ints { - PB1200_INT_BEGIN = AU1000_MAX_INTR + 1, - - PB1200_IDE_INT = PB1200_INT_BEGIN, - PB1200_ETH_INT, - PB1200_PC0_INT, - PB1200_PC0_STSCHG_INT, - PB1200_PC1_INT, - PB1200_PC1_STSCHG_INT, - PB1200_DC_INT, - PB1200_FLASHBUSY_INT, - PB1200_PC0_INSERT_INT, - PB1200_PC0_EJECT_INT, - PB1200_PC1_INSERT_INT, - PB1200_PC1_EJECT_INT, - PB1200_SD0_INSERT_INT, - PB1200_SD0_EJECT_INT, - PB1200_SD1_INSERT_INT, - PB1200_SD1_EJECT_INT, - - PB1200_INT_END = PB1200_INT_BEGIN + 15 -}; - -/* NAND chip select */ -#define NAND_CS 1 - -#endif /* __ASM_PB1200_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h deleted file mode 100644 index 443b88adebf..00000000000 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * AMD Alchemy Semi PB1550 Reference Board - * Board Registers defines. - * - * Copyright 2004 Embedded Edge LLC. - * Copyright 2005 Ralf Baechle (ralf@linux-mips.org) - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_PB1550_H -#define __ASM_PB1550_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR -#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR -#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR - -/* - * Timing values as described in databook, * ns value stripped of - * lower 2 bits. - * These defines are here rather than an SOC1550 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) - -#define NAND_CS 1 - -/* Should be done by YAMON */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ - -#endif /* __ASM_PB1550_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c7d3cf1ce46..98383995e6a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1014,6 +1014,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) { decode_configs(c); + if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { + c->cputype = CPU_ALCHEMY; + __cpu_name[cpu] = "Au1300"; + /* following stuff is not for Alchemy */ + return; + } + c->options = (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_COUNTER | |