diff options
author | David Howells <dhowells@redhat.com> | 2012-03-28 18:30:02 +0100 |
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committer | David Howells <dhowells@redhat.com> | 2012-03-28 18:30:02 +0100 |
commit | 527dcdccd60759ee38e6224c93f87a6194d970ad (patch) | |
tree | 3c62af76210b19d819b5204108b41a3e8054e755 /arch/parisc/include/asm/barrier.h | |
parent | 1c80f22f8d809a9a9024aad7a5bd093f078e77cf (diff) |
Disintegrate asm/system.h for PA-RISC
Disintegrate asm/system.h for PA-RISC.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: linux-parisc@vger.kernel.org
Diffstat (limited to 'arch/parisc/include/asm/barrier.h')
-rw-r--r-- | arch/parisc/include/asm/barrier.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/parisc/include/asm/barrier.h b/arch/parisc/include/asm/barrier.h new file mode 100644 index 00000000000..e77d834aa80 --- /dev/null +++ b/arch/parisc/include/asm/barrier.h @@ -0,0 +1,35 @@ +#ifndef __PARISC_BARRIER_H +#define __PARISC_BARRIER_H + +/* +** This is simply the barrier() macro from linux/kernel.h but when serial.c +** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h +** hasn't yet been included yet so it fails, thus repeating the macro here. +** +** PA-RISC architecture allows for weakly ordered memory accesses although +** none of the processors use it. There is a strong ordered bit that is +** set in the O-bit of the page directory entry. Operating systems that +** can not tolerate out of order accesses should set this bit when mapping +** pages. The O-bit of the PSW should also be set to 1 (I don't believe any +** of the processor implemented the PSW O-bit). The PCX-W ERS states that +** the TLB O-bit is not implemented so the page directory does not need to +** have the O-bit set when mapping pages (section 3.1). This section also +** states that the PSW Y, Z, G, and O bits are not implemented. +** So it looks like nothing needs to be done for parisc-linux (yet). +** (thanks to chada for the above comment -ggg) +** +** The __asm__ op below simple prevents gcc/ld from reordering +** instructions across the mb() "call". +*/ +#define mb() __asm__ __volatile__("":::"memory") /* barrier() */ +#define rmb() mb() +#define wmb() mb() +#define smp_mb() mb() +#define smp_rmb() mb() +#define smp_wmb() mb() +#define smp_read_barrier_depends() do { } while(0) +#define read_barrier_depends() do { } while(0) + +#define set_mb(var, value) do { var = value; mb(); } while (0) + +#endif /* __PARISC_BARRIER_H */ |