diff options
| author | Tiejun Chen <tiejun.chen@windriver.com> | 2009-08-22 16:03:43 +0000 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2009-08-31 09:20:55 -0400 |
| commit | 0484c1df473815020bdce4b46b861395759686e5 (patch) | |
| tree | de1f24a25008b874edbe3c94c88717ba4b5b6424 /arch/powerpc/boot/dcr.h | |
| parent | 0cdf50a7c65df894fb5fd0ef181fe18b8fec6137 (diff) | |
powerpc/405ex: provide necessary fixup function to support cuImage
For cuImage format it's necessary to provide clock fixups since u-boot will
not pass necessary clock frequency into the dtb included into cuImage so we
implement the clock fixups as defined in the technical documentation for the
board and update header file with the basic register definitions.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dcr.h')
| -rw-r--r-- | arch/powerpc/boot/dcr.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 95b9f534401..645a7c964e5 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -153,9 +153,7 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, #define DCRN_CPC0_PLLMR1 0xf4 #define DCRN_CPC0_UCR 0xf5 -/* 440GX Clock control etc */ - - +/* 440GX/405EX Clock Control reg */ #define DCRN_CPR0_CLKUPD 0x020 #define DCRN_CPR0_PLLC 0x040 #define DCRN_CPR0_PLLD 0x060 |