[POWERPC] Move PCI nodes to be sibilings with SOC nodes

Updated the device trees to have the PCI nodes be at the same level as
the SOC node.  This is to make it so that the SOC nodes children address
space is just on chip registers and not other bus memory as well.

Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge
that exists in the PHB.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 95 insertions, 95 deletions

diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 98afd4df27b..6633e07d9f4 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -43,7 +43,7 @@
 		#size-cells = <1>;
 		device_type = "soc";
 		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00100000>;	// CCSRBAR 1M
+		reg = <e0000000 00001000>;	// CCSRBAR 1M
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
@@ -135,100 +135,6 @@
 			interrupt-parent = <&mpic>;
 		};
 
-		pci1: pci@8000 {
-			interrupt-map-mask = <1f800 0 0 7>;
-			interrupt-map = <
-
-				/* IDSEL 0x10 */
-				08000 0 0 1 &mpic 0 1
-				08000 0 0 2 &mpic 1 1
-				08000 0 0 3 &mpic 2 1
-				08000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x11 */
-				08800 0 0 1 &mpic 0 1
-				08800 0 0 2 &mpic 1 1
-				08800 0 0 3 &mpic 2 1
-				08800 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x12 (Slot 1) */
-				09000 0 0 1 &mpic 0 1
-				09000 0 0 2 &mpic 1 1
-				09000 0 0 3 &mpic 2 1
-				09000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x13 (Slot 2) */
-				09800 0 0 1 &mpic 1 1
-				09800 0 0 2 &mpic 2 1
-				09800 0 0 3 &mpic 3 1
-				09800 0 0 4 &mpic 0 1
-
-				/* IDSEL 0x14 (Slot 3) */
-				0a000 0 0 1 &mpic 2 1
-				0a000 0 0 2 &mpic 3 1
-				0a000 0 0 3 &mpic 0 1
-				0a000 0 0 4 &mpic 1 1
-
-				/* IDSEL 0x15 (Slot 4) */
-				0a800 0 0 1 &mpic 3 1
-				0a800 0 0 2 &mpic 0 1
-				0a800 0 0 3 &mpic 1 1
-				0a800 0 0 4 &mpic 2 1
-
-				/* Bus 1 (Tundra Bridge) */
-				/* IDSEL 0x12 (ISA bridge) */
-				19000 0 0 1 &mpic 0 1
-				19000 0 0 2 &mpic 1 1
-				19000 0 0 3 &mpic 2 1
-				19000 0 0 4 &mpic 3 1>;
-			interrupt-parent = <&mpic>;
-			interrupts = <18 2>;
-			bus-range = <0 0>;
-			ranges = <02000000 0 80000000 80000000 0 20000000
-				  01000000 0 00000000 e2000000 0 00100000>;
-			clock-frequency = <3f940aa>;
-			#interrupt-cells = <1>;
-			#size-cells = <2>;
-			#address-cells = <3>;
-			reg = <8000 1000>;
-			compatible = "fsl,mpc8540-pci";
-			device_type = "pci";
-
-			i8259@19000 {
-				interrupt-controller;
-				device_type = "interrupt-controller";
-				reg = <19000 0 0 0 1>;
-				#address-cells = <0>;
-				#interrupt-cells = <2>;
-				compatible = "chrp,iic";
-				interrupts = <1>;
-				interrupt-parent = <&pci1>;
-			};
-		};
-
-		pci@9000 {
-			interrupt-map-mask = <f800 0 0 7>;
-			interrupt-map = <
-
-				/* IDSEL 0x15 */
-				a800 0 0 1 &mpic b 1
-				a800 0 0 2 &mpic b 1
-				a800 0 0 3 &mpic b 1
-				a800 0 0 4 &mpic b 1>;
-			interrupt-parent = <&mpic>;
-			interrupts = <19 2>;
-			bus-range = <0 0>;
-			ranges = <02000000 0 a0000000 a0000000 0 20000000
-				  01000000 0 00000000 e3000000 0 00100000>;
-			clock-frequency = <3f940aa>;
-			#interrupt-cells = <1>;
-			#size-cells = <2>;
-			#address-cells = <3>;
-			reg = <9000 1000>;
-			compatible = "fsl,mpc8540-pci";
-			device_type = "pci";
-		};
-
 		mpic: pic@40000 {
 			clock-frequency = <0>;
 			interrupt-controller;
@@ -240,4 +146,98 @@
                         big-endian;
 		};
 	};
+
+	pci1: pci@e0008000 {
+		interrupt-map-mask = <1f800 0 0 7>;
+		interrupt-map = <
+
+			/* IDSEL 0x10 */
+			08000 0 0 1 &mpic 0 1
+			08000 0 0 2 &mpic 1 1
+			08000 0 0 3 &mpic 2 1
+			08000 0 0 4 &mpic 3 1
+
+			/* IDSEL 0x11 */
+			08800 0 0 1 &mpic 0 1
+			08800 0 0 2 &mpic 1 1
+			08800 0 0 3 &mpic 2 1
+			08800 0 0 4 &mpic 3 1
+
+			/* IDSEL 0x12 (Slot 1) */
+			09000 0 0 1 &mpic 0 1
+			09000 0 0 2 &mpic 1 1
+			09000 0 0 3 &mpic 2 1
+			09000 0 0 4 &mpic 3 1
+
+			/* IDSEL 0x13 (Slot 2) */
+			09800 0 0 1 &mpic 1 1
+			09800 0 0 2 &mpic 2 1
+			09800 0 0 3 &mpic 3 1
+			09800 0 0 4 &mpic 0 1
+
+			/* IDSEL 0x14 (Slot 3) */
+			0a000 0 0 1 &mpic 2 1
+			0a000 0 0 2 &mpic 3 1
+			0a000 0 0 3 &mpic 0 1
+			0a000 0 0 4 &mpic 1 1
+
+			/* IDSEL 0x15 (Slot 4) */
+			0a800 0 0 1 &mpic 3 1
+			0a800 0 0 2 &mpic 0 1
+			0a800 0 0 3 &mpic 1 1
+			0a800 0 0 4 &mpic 2 1
+
+			/* Bus 1 (Tundra Bridge) */
+			/* IDSEL 0x12 (ISA bridge) */
+			19000 0 0 1 &mpic 0 1
+			19000 0 0 2 &mpic 1 1
+			19000 0 0 3 &mpic 2 1
+			19000 0 0 4 &mpic 3 1>;
+		interrupt-parent = <&mpic>;
+		interrupts = <18 2>;
+		bus-range = <0 0>;
+		ranges = <02000000 0 80000000 80000000 0 20000000
+			  01000000 0 00000000 e2000000 0 00100000>;
+		clock-frequency = <3f940aa>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <e0008000 1000>;
+		compatible = "fsl,mpc8540-pci";
+		device_type = "pci";
+
+		i8259@19000 {
+			interrupt-controller;
+			device_type = "interrupt-controller";
+			reg = <19000 0 0 0 1>;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "chrp,iic";
+			interrupts = <1>;
+			interrupt-parent = <&pci1>;
+		};
+	};
+
+	pci@e0009000 {
+		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map = <
+
+			/* IDSEL 0x15 */
+			a800 0 0 1 &mpic b 1
+			a800 0 0 2 &mpic b 1
+			a800 0 0 3 &mpic b 1
+			a800 0 0 4 &mpic b 1>;
+		interrupt-parent = <&mpic>;
+		interrupts = <19 2>;
+		bus-range = <0 0>;
+		ranges = <02000000 0 a0000000 a0000000 0 20000000
+			  01000000 0 00000000 e3000000 0 00100000>;
+		clock-frequency = <3f940aa>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <e0009000 1000>;
+		compatible = "fsl,mpc8540-pci";
+		device_type = "pci";
+	};
 };