[POWERPC] Move PCI nodes to be sibilings with SOC nodes

Updated the device trees to have the PCI nodes be at the same level as
the SOC node.  This is to make it so that the SOC nodes children address
space is just on chip registers and not other bus memory as well.

Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge
that exists in the PHB.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 196 insertions, 176 deletions

diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 88082ac6f2c..3f9d15cf13e 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -43,16 +43,7 @@
 		#size-cells = <1>;
 		device_type = "soc";
 
-
-		ranges = <00001000 e0001000 000ff000
-			  80000000 80000000 20000000
-			  a0000000 a0000000 10000000
-			  b0000000 b0000000 00100000
-			  c0000000 c0000000 20000000
-			  b0100000 b0100000 00100000
-			  e1000000 e1000000 00010000
-			  e1010000 e1010000 00010000
-			  e1020000 e1020000 00010000>;
+		ranges = <00000000 e0000000 00100000>;
 		reg = <e0000000 00001000>;	// CCSRBAR 1M
 		bus-frequency = <0>;		// Filled out by uboot.
 
@@ -147,115 +138,173 @@
 			interrupt-parent = <&mpic>;
 		};
 
-		pci@8000 {
-			compatible = "fsl,mpc8540-pci";
-			device_type = "pci";
-			interrupt-map-mask = <f800 0 0 7>;
-			interrupt-map = <
-
-				/* IDSEL 0x11 J17 Slot 1 */
-				8800 0 0 1 &mpic 2 1
-				8800 0 0 2 &mpic 3 1
-				8800 0 0 3 &mpic 4 1
-				8800 0 0 4 &mpic 1 1
+		global-utilities@e0000 {	//global utilities block
+			compatible = "fsl,mpc8548-guts";
+			reg = <e0000 1000>;
+			fsl,has-rstcr;
+		};
 
-				/* IDSEL 0x12 J16 Slot 2 */
+		mpic: pic@40000 {
+			clock-frequency = <0>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <40000 40000>;
+			compatible = "chrp,open-pic";
+			device_type = "open-pic";
+			big-endian;
+		};
+	};
 
-				9000 0 0 1 &mpic 3 1
-				9000 0 0 2 &mpic 4 1
-				9000 0 0 3 &mpic 2 1
-				9000 0 0 4 &mpic 1 1>;
+	pci@e0008000 {
+		compatible = "fsl,mpc8540-pci";
+		device_type = "pci";
+		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map = <
+
+			/* IDSEL 0x11 J17 Slot 1 */
+			8800 0 0 1 &mpic 2 1
+			8800 0 0 2 &mpic 3 1
+			8800 0 0 3 &mpic 4 1
+			8800 0 0 4 &mpic 1 1
+
+			/* IDSEL 0x12 J16 Slot 2 */
+
+			9000 0 0 1 &mpic 3 1
+			9000 0 0 2 &mpic 4 1
+			9000 0 0 3 &mpic 2 1
+			9000 0 0 4 &mpic 1 1>;
+
+		interrupt-parent = <&mpic>;
+		interrupts = <18 2>;
+		bus-range = <0 ff>;
+		ranges = <02000000 0 c0000000 c0000000 0 20000000
+			  01000000 0 00000000 e1000000 0 00010000>;
+		clock-frequency = <3f940aa>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <e0008000 1000>;
+	};
 
-			interrupt-parent = <&mpic>;
-			interrupts = <18 2>;
-			bus-range = <0 ff>;
-			ranges = <02000000 0 c0000000 c0000000 0 20000000
-				  01000000 0 00000000 e1000000 0 00010000>;
-			clock-frequency = <3f940aa>;
-			#interrupt-cells = <1>;
+	pcie@e0009000 {
+		compatible = "fsl,mpc8548-pcie";
+		device_type = "pci";
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <e0009000 1000>;
+		bus-range = <0 ff>;
+		ranges = <02000000 0 80000000 80000000 0 20000000
+			  01000000 0 00000000 e1010000 0 00010000>;
+		clock-frequency = <1fca055>;
+		interrupt-parent = <&mpic>;
+		interrupts = <1a 2>;
+		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 4 1
+			0000 0 0 2 &mpic 5 1
+			0000 0 0 3 &mpic 6 1
+			0000 0 0 4 &mpic 7 1
+			>;
+		pcie@0 {
+			reg = <0 0 0 0 0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = <8000 1000>;
-		};
-
-		pcie@9000 {
-			compatible = "fsl,mpc8548-pcie";
 			device_type = "pci";
-			#interrupt-cells = <1>;
-			#size-cells = <2>;
-			#address-cells = <3>;
-			reg = <9000 1000>;
-			bus-range = <0 ff>;
-			ranges = <02000000 0 80000000 80000000 0 20000000
-				  01000000 0 00000000 e1010000 0 00010000>;
-			clock-frequency = <1fca055>;
-			interrupt-parent = <&mpic>;
-			interrupts = <1a 2>;
-			interrupt-map-mask = <f800 0 0 7>;
-			interrupt-map = <
-				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 4 1
-				0000 0 0 2 &mpic 5 1
-				0000 0 0 3 &mpic 6 1
-				0000 0 0 4 &mpic 7 1
-				>;
+			ranges = <02000000 0 80000000
+				  02000000 0 80000000
+				  0 20000000
+
+				  01000000 0 00000000
+				  01000000 0 00000000
+				  0 00010000>;
 		};
+	};
 
-		pcie@a000 {
-			compatible = "fsl,mpc8548-pcie";
-			device_type = "pci";
-			#interrupt-cells = <1>;
+	pcie@e000a000 {
+		compatible = "fsl,mpc8548-pcie";
+		device_type = "pci";
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <e000a000 1000>;
+		bus-range = <0 ff>;
+		ranges = <02000000 0 a0000000 a0000000 0 10000000
+			  01000000 0 00000000 e1020000 0 00010000>;
+		clock-frequency = <1fca055>;
+		interrupt-parent = <&mpic>;
+		interrupts = <19 2>;
+		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 0 1
+			0000 0 0 2 &mpic 1 1
+			0000 0 0 3 &mpic 2 1
+			0000 0 0 4 &mpic 3 1
+			>;
+		pcie@0 {
+			reg = <0 0 0 0 0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = <a000 1000>;
-			bus-range = <0 ff>;
-			ranges = <02000000 0 a0000000 a0000000 0 10000000
-				  01000000 0 00000000 e1020000 0 00010000>;
-			clock-frequency = <1fca055>;
-			interrupt-parent = <&mpic>;
-			interrupts = <19 2>;
-			interrupt-map-mask = <f800 0 0 7>;
-			interrupt-map = <
-				/* IDSEL 0x0 */
-				0000 0 0 1 &mpic 0 1
-				0000 0 0 2 &mpic 1 1
-				0000 0 0 3 &mpic 2 1
-				0000 0 0 4 &mpic 3 1
-				>;
+			device_type = "pci";
+			ranges = <02000000 0 a0000000
+				  02000000 0 a0000000
+				  0 10000000
+
+				  01000000 0 00000000
+				  01000000 0 00000000
+				  0 00010000>;
 		};
+	};
 
-		pcie@b000 {
-			compatible = "fsl,mpc8548-pcie";
-			device_type = "pci";
-			#interrupt-cells = <1>;
+	pcie@e000b000 {
+		compatible = "fsl,mpc8548-pcie";
+		device_type = "pci";
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <e000b000 1000>;
+		bus-range = <0 ff>;
+		ranges = <02000000 0 b0000000 b0000000 0 00100000
+			  01000000 0 00000000 b0100000 0 00100000>;
+		clock-frequency = <1fca055>;
+		interrupt-parent = <&mpic>;
+		interrupts = <1b 2>;
+		interrupt-map-mask = <fb00 0 0 0>;
+		interrupt-map = <
+			// IDSEL 0x1c  USB
+			e000 0 0 0 &i8259 c 2
+			e100 0 0 0 &i8259 9 2
+			e200 0 0 0 &i8259 a 2
+			e300 0 0 0 &i8259 b 2
+
+			// IDSEL 0x1d  Audio
+			e800 0 0 0 &i8259 6 2
+
+			// IDSEL 0x1e Legacy
+			f000 0 0 0 &i8259 7 2
+			f100 0 0 0 &i8259 7 2
+
+			// IDSEL 0x1f IDE/SATA
+			f800 0 0 0 &i8259 e 2
+			f900 0 0 0 &i8259 5 2
+		>;
+
+		pcie@0 {
+			reg = <0 0 0 0 0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = <b000 1000>;
-			bus-range = <0 ff>;
-			ranges = <02000000 0 b0000000 b0000000 0 00100000
-				  01000000 0 00000000 b0100000 0 00100000>;
-			clock-frequency = <1fca055>;
-			interrupt-parent = <&mpic>;
-			interrupts = <1b 2>;
-			interrupt-map-mask = <fb00 0 0 0>;
-			interrupt-map = <
-				// IDSEL 0x1c  USB
-				e000 0 0 0 &i8259 c 2
-				e100 0 0 0 &i8259 9 2
-				e200 0 0 0 &i8259 a 2
-				e300 0 0 0 &i8259 b 2
-
-				// IDSEL 0x1d  Audio
-				e800 0 0 0 &i8259 6 2
-
-				// IDSEL 0x1e Legacy
-				f000 0 0 0 &i8259 7 2
-				f100 0 0 0 &i8259 7 2
-
-				// IDSEL 0x1f IDE/SATA
-				f800 0 0 0 &i8259 e 2
-				f900 0 0 0 &i8259 5 2
-			>;
+			device_type = "pci";
+			ranges = <02000000 0 b0000000
+				  02000000 0 b0000000
+				  0 00100000
+
+				  01000000 0 00000000
+				  01000000 0 00000000
+				  0 00100000>;
+
 			uli1575@0 {
 				reg = <0 0 0 0 0>;
 				#size-cells = <2>;
@@ -263,92 +312,63 @@
 				ranges = <02000000 0 b0000000
 					  02000000 0 b0000000
 					  0 00100000
+
 					  01000000 0 00000000
 					  01000000 0 00000000
 					  0 00100000>;
-
-				pci_bridge@0 {
-					reg = <0 0 0 0 0>;
-					#size-cells = <2>;
-					#address-cells = <3>;
-					ranges = <02000000 0 b0000000
-						  02000000 0 b0000000
-						  0 00100000
-						  01000000 0 00000000
-						  01000000 0 00000000
-						  0 00100000>; 
-
-					isa@1e {
-						device_type = "isa";
+				isa@1e {
+					device_type = "isa";
+					#interrupt-cells = <2>;
+					#size-cells = <1>;
+					#address-cells = <2>;
+					reg = <f000 0 0 0 0>;
+					ranges = <1 0
+						  01000000 0 0
+						  00001000>;
+					interrupt-parent = <&i8259>;
+
+					i8259: interrupt-controller@20 {
+						reg = <1 20 2
+						       1 a0 2
+						       1 4d0 2>;
+						interrupt-controller;
+						device_type = "interrupt-controller";
+						#address-cells = <0>;
 						#interrupt-cells = <2>;
-						#size-cells = <1>;
-						#address-cells = <2>;
-						reg = <f000 0 0 0 0>;
-						ranges = <1 0
-							  01000000 0 0
-							  00001000>;
+						compatible = "chrp,iic";
+						interrupts = <9 2>;
+						interrupt-parent = <&mpic>;
+					};
+
+					i8042@60 {
+						#size-cells = <0>;
+						#address-cells = <1>;
+						reg = <1 60 1 1 64 1>;
+						interrupts = <1 3 c 3>;
 						interrupt-parent = <&i8259>;
 
-						i8259: interrupt-controller@20 {
-							reg = <1 20 2
-							       1 a0 2
-							       1 4d0 2>;
-							interrupt-controller;
-							device_type = "interrupt-controller";
-							#address-cells = <0>;
-							#interrupt-cells = <2>;
-							compatible = "chrp,iic";
-							interrupts = <9 2>;
-							interrupt-parent = <&mpic>;
+						keyboard@0 {
+							reg = <0>;
+							compatible = "pnpPNP,303";
 						};
 
-						i8042@60 {
-							#size-cells = <0>;
-							#address-cells = <1>;
-							reg = <1 60 1 1 64 1>;
-							interrupts = <1 3 c 3>;
-							interrupt-parent = <&i8259>;
-
-							keyboard@0 {
-								reg = <0>;
-								compatible = "pnpPNP,303";
-							};
-
-							mouse@1 {
-								reg = <1>;
-								compatible = "pnpPNP,f03";
-							};
+						mouse@1 {
+							reg = <1>;
+							compatible = "pnpPNP,f03";
 						};
+					};
 
-						rtc@70 {
-							compatible = "pnpPNP,b00";
-							reg = <1 70 2>;
-						};
+					rtc@70 {
+						compatible = "pnpPNP,b00";
+						reg = <1 70 2>;
+					};
 
-						gpio@400 {
-							reg = <1 400 80>;
-						};
+					gpio@400 {
+						reg = <1 400 80>;
 					};
 				};
 			};
-
 		};
 
-		global-utilities@e0000 {	//global utilities block
-			compatible = "fsl,mpc8548-guts";
-			reg = <e0000 1000>;
-			fsl,has-rstcr;
-		};
-
-		mpic: pic@40000 {
-			clock-frequency = <0>;
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <2>;
-			reg = <40000 40000>;
-			compatible = "chrp,open-pic";
-			device_type = "open-pic";
-			big-endian;
-		};
 	};
 };