diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2007-07-03 02:35:35 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-07-03 02:35:35 -0500 |
| commit | b533f8ae796d1ee0289bf04d4f1e72c02ad4a17d (patch) | |
| tree | 4bec480194b251e18fee511df1cf4840a1995c88 /arch/powerpc/boot/dts/mpc8641_hpcn.dts | |
| parent | eae98266e78e5659d75dbb62b4601960c15c7830 (diff) | |
[POWERPC] Reworked interrupt numbers for OpenPIC based Freescale chips
Make the interrupt numbers match the OpenPIC spec intead of the
Freescale docs which distinguish between internal and external interrupts.
Now we can use the interrupt number directly to find the register offset
associated with it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8641_hpcn.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8641_hpcn.dts | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 4b8ac7231ac..db56a02b748 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -90,25 +90,25 @@ reg = <24520 20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; - interrupts = <4a 1>; + interrupts = <a 1>; reg = <0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; - interrupts = <4a 1>; + interrupts = <a 1>; reg = <1>; device_type = "ethernet-phy"; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; - interrupts = <4a 1>; + interrupts = <a 1>; reg = <2>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; - interrupts = <4a 1>; + interrupts = <a 1>; reg = <3>; device_type = "ethernet-phy"; }; @@ -356,7 +356,7 @@ #interrupt-cells = <2>; built-in; compatible = "chrp,iic"; - interrupts = <49 2>; + interrupts = <9 2>; interrupt-parent = <&mpic>; }; @@ -411,10 +411,10 @@ interrupt-map-mask = <f800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 44 1 - 0000 0 0 2 &mpic 45 1 - 0000 0 0 3 &mpic 46 1 - 0000 0 0 4 &mpic 47 1 + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 >; }; |