diff options
| author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2012-03-15 18:40:28 +0100 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-03-16 10:46:31 -0500 |
| commit | 564ee46fb7b3d1cb9214ab32dde60cbe044b1f16 (patch) | |
| tree | 7c183cfbdbfc59f9477b2137287b2bb4e7112341 /arch/powerpc/boot/dts/p2020rdb.dts | |
| parent | 0c00f65653389a408dfbbee7578e671664eea26a (diff) | |
powerpc/85xx: p2020rdb & p1010rdb - lower spi flash freq to 40Mhz
This is here most likely since the FSL bsp. Back in the FSL bsp it was
set to 50Mhz and working. However the driver divided the SoC freq. only
by 2. According to the TRM the platform clock (which the manual refers
in its formula) is the system clock divided by two. So in the end it has
to divide by 4 and this is what the fsl-spi driver in tree is doing.
Since then the flash is not wokring I guess. After chaning the freq from
50Mhz to 40Mhz like others do then I can access the flash.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/p2020rdb.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/p2020rdb.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts index 8f25ef2e6e4..153bc76bb48 100644 --- a/arch/powerpc/boot/dts/p2020rdb.dts +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -157,7 +157,7 @@ #size-cells = <1>; compatible = "spansion,s25sl12801"; reg = <0>; - spi-max-frequency = <50000000>; + spi-max-frequency = <40000000>; partition@0 { /* 512KB for u-boot Bootloader Image */ |