diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2011-11-04 09:47:49 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-11-24 02:01:39 -0600 |
| commit | b9db022c62f72bc5a029f20851b012895a6ea7ca (patch) | |
| tree | fdd6987a68f4857280d9fc215ba3b0b44c2c2811 /arch/powerpc/boot/dts/p4080ds.dts | |
| parent | 8389c823b50bfb81eccdb115f486459adacf4b17 (diff) | |
powerpc/85xx: Rework P4080DS device trees
Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.
Other changes include:
* Adding of MPIC timer blocks
* Dropping "fsl,p4080-IP..." from compatibles for standard blocks
* Removed mpic interrupt-parent from dcsr-epu node, just use top level
* Removed mpic interrupt-parent from sec nodes, just use top level
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/p4080ds.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/p4080ds.dts | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts index c7916dc2801..8ea1ae90815 100644 --- a/arch/powerpc/boot/dts/p4080ds.dts +++ b/arch/powerpc/boot/dts/p4080ds.dts @@ -32,7 +32,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/include/ "p4080si.dtsi" +/include/ "fsl/p4080si-pre.dtsi" / { model = "fsl,P4080DS"; @@ -50,6 +50,9 @@ }; soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + spi@110000 { flash@0 { #address-cells = <1>; @@ -105,12 +108,12 @@ }; }; - rapidio0: rapidio@ffe0c0000 { + rio: rapidio0: rapidio@ffe0c0000 { reg = <0xf 0xfe0c0000 0 0x20000>; ranges = <0 0 0xc 0x20000000 0 0x01000000>; }; - localbus@ffe124000 { + lbc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x1000>; ranges = <0 0 0xf 0xe8000000 0x08000000 3 0 0xf 0xffdf0000 0x00008000>; @@ -132,6 +135,7 @@ reg = <0xf 0xfe200000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; + fsl,msi = <&msi0>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -147,6 +151,7 @@ reg = <0xf 0xfe201000 0 0x1000>; ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; + fsl,msi = <&msi1>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -162,6 +167,7 @@ reg = <0xf 0xfe202000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + fsl,msi = <&msi2>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -174,3 +180,5 @@ }; }; + +/include/ "fsl/p4080si-post.dtsi" |