diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-07-18 22:50:34 +0200 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-07-18 22:50:34 +0200 |
commit | a208f37a465e222218974ab20a31b42b7b4893b2 (patch) | |
tree | 77c6acdd4be32024330a14f2618b814126ce7a20 /arch/powerpc/boot/dts/stx_gp3_8560.dts | |
parent | 511d9d34183662aada3890883e860b151d707e22 (diff) | |
parent | 5b664cb235e97afbf34db9c4d77f08ebd725335e (diff) |
Merge branch 'linus' into x86/x2apic
Diffstat (limited to 'arch/powerpc/boot/dts/stx_gp3_8560.dts')
-rw-r--r-- | arch/powerpc/boot/dts/stx_gp3_8560.dts | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index f81fd7fdb29..fcd1db6ca0a 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -38,6 +38,7 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + next-level-cache = <&L2>; }; }; @@ -62,7 +63,7 @@ interrupts = <18 2>; }; - l2-cache-controller@20000 { + L2: l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; @@ -82,6 +83,47 @@ dfsrr; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8560-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -131,6 +173,7 @@ #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; device_type = "open-pic"; }; |